
Memory Management
2-15
Wait states extend the amount of time the read- or write-command signal is asserted for
memory or I/O accesses. This has the effect of increasing the total length of the cycle.
Table 2-9 on page 2-15 documents the number of wait states for the various ROM-DOS,
ROM-BIOS and ISA cycles.
2.5.3
High-Speed Clock ROM Cycles
To improve the ROM-access times, an option is provided so that accesses using the
ROMCS or DOSCS chip selects may run at the high-speed CPU clock rate rather than
the low-speed CPU clock rate of 9.2 MHz.
2.5.4
ROM Chip-Select Signal
The high-speed CPU clock rate is enabled for the ROM Chip-Select (ROMCS) signal and
unique wait-state controls for each ROM chip-select may be programmed through the
Miscellaneous 5 register at Index B3h.
I
Bit 6 of the Miscellaneous 5 register at Index B3h
accesses to run at the high-speed CPU clock rate as follows:
Enables ROMCS ROM
— 0
Disabled (default)
— 1
Enabled
I
Bits 5 and 4 of the Miscellaneous 5 register at Index B3h
wait states for fast ROMCS cycles (see Table 2-10 on page 2-16).
Control the number of
Table 2-9
Wait States for Various Cycles
Cycle Type
Number of Wait States (in SYSCLK Cycles)
8-bit ISA memory
8-bit ROM BIOS (MMS-accessed)
2, 3, 4, or 5 (determined by bits 0 and 1 of the MMS Memory
Wait State 1 register at Index 62h)
8-bit ROM DOS
(MMS accessed and linearly decoded)
1, 2, 3, 4, or ISA setting (determined by bits 2–0 of the MMS
Memory Wait State 2 register)
8-bit ROM BIOS (not MMS accessed)
2 or 3 (determined by bits 7 and 4 of the Command Delay
register at Index 60h)
16-bit ROM-DOS, ROM-BIOS and ISA
memory
1, 2, 3, or 4 (determined by bits 3 and 2 of the MMS Memory
Wait State 1 register)
8-bit internal I/O (000–0FFh)
2 or 4 (determined by bit 3 of the Wait State Control register at
Index 63h)
8-bit floppy-disk-drive I/O (3F0–3F7h)
2, 3, 4, or 5 (determined by bits 1 and 0 of the I/O Wait State
register at Index 61h)
8-bit hard-disk-drive I/O (1F0–1F7h)
2, 3, 4, or 5 (determined by bits 3 and 2 of the I/O Wait State
register)
Other 8-bit I/O (100–3FFh)
2, 3, 4, or 5 (determined by bits 5 and 4 of the I/O Wait State
register)
16-bit I/O
3 or 4 (determined by bit 2 of the Wait State Control register)