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參數(shù)資料
| 型號： | 20665 |
| 英文描述： | ?lanSC310 Programmer＇s Reference Manual |
| 中文描述： | ？lanSC310程序員參考手冊 |
| 文件頁數(shù)： | 51/186頁 |
| 文件大?。?/td> | 918K |
| 代理商： | 20665 |
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1-40
Power Management
1.10
AUTO LOW-SPEED LOGIC
The élanSC310 microcontroller’s auto low-speed logic provides a way for the system
designer to fine-tune the system’s current consumption in High-Speed PLL mode. Auto
Low-Speed mode is enabled by setting bit 3 of the Control B register at Index 77h. Auto
Low-Speed mode has no effect unless the high-speed clock is enabled at bit 6 of the I/O
Wait State register at Index 61h. When enabled, the auto low-speed logic causes the use
of the high-speed clock to be disallowed at periodic intervals when in High-Speed PLL
mode. During the active trigger period, all bus cycles are performed at 9.2 MHz in High-
Speed PLL mode. There is no effect in any other PMU mode. The start and end of the
low-speed interval is synchronized with refresh. To program the trigger and duration peri-
ods, see “Auto Low-Speed Control Register (Index 9Fh)” on page 4-51.
1.11
MICRO POWER-OFF MODE
The Micro Power-Off feature of the élanSC310 microcontroller should not be confused
with a PMU mode or state such as High-Speed PLL mode, Low-Speed PLL mode, or
Suspend mode.
There is no software processing required or available to enter the Micro Power-Off
mode. For most applications, Micro Power-Off mode is like completely turning off the
power to the system while maintaining real-time clock operation and CMOS contents.
The system enters Micro Power-Off mode
immediately when the IORESET pin is sam-
pled Low. There is no option to generate an SMI or NMI to save the system state upon
detection of IORESET being asserted.
The type of micro power-off DRAM refresh performed (CAS-before-RAS, or self-refresh)
is the same as that for which the part was configured (via bit 3 of the Miscellaneous 5
register at Index B3h) prior to sampling the IORESET pin Low.
Exiting Micro Power-Off mode is analogous to a power-up cold boot, with the exception
that the bits shown below remain set to their previously programmed values. The configu-
ration-register bits that are not reset when exiting Micro Power-Off mode are as follows:
I
Bits 1–0 of the Version register at Index 64h
I
Bits 7–0 of the Clock Control register at Index 8Fh
I
Bits 7–4 and 2–0 of the Reserved register at Index 9Dh
I
Bit 1 of the PMU Control 1 register at Index A7h
I
Bit 3 of the Miscellaneous 5 register at Index B3h
I
Bits 4–0 of the Miscellaneous 3 register at Index BAh
The one software option that relates to Micro Power-Off mode is whether the DRAM con-
tents will be maintained along with the CMOS/RTC functions mentioned in the preceding
paragraph. This option is enabled by setting bit 2 of the Miscellaneous 3 register at
Index BAh. This bit is cleared upon core reset, using the RESIN pin. IORESET has no
effect on this bit. The bit may be used by system firmware to determine whether or not
DRAM has been retained after an IORESET has occurred.
For more information on the Micro Power-Off mode, see the élanSC310 Microcontroller
Data Sheet, PID 20668.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 20668 | ?lanSC300 Data Sheet ?lanSC310 Data Sheet |
| 2067 | SAFETY SWITCH FERROCODE |
| 2070 | SAFETY SWITCH FERROCODE |
| 2068 | SAFETY SWITCH FERROCODE |
| 2068-6104-015 | Flange Mount Medium Power Terminations |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 20-665000-00 | 功能描述:IC 與器件插座 SOWIC TO SOIC ADAPT 20 PINS RoHS:否 制造商:Molex 產(chǎn)品:LGA Sockets 節(jié)距:1.02 mm 排數(shù): 位置/觸點數(shù)量:2011 觸點電鍍:Gold 安裝風格:SMD/SMT 端接類型:Solder 插座/封裝類型:LGA 2011 工作溫度范圍:- 40 C to + 100 C |
| 20-665000-00-P | 制造商:ARIES 制造商全稱:Aries Electronics, Inc. 功能描述:SOWI-to-SOIC Adapter |
| 206650-1 | 制造商:TE Connectivity 功能描述:206650-1 |
| 2066531 | 制造商: 功能描述: 制造商:TE Connectivity 功能描述: 制造商:undefined 功能描述: |
| 206653-1 | 制造商: 功能描述: 制造商:undefined 功能描述: |
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