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| 型號(hào)： | 20665 |
| 英文描述： | ?lanSC310 Programmer＇s Reference Manual |
| 中文描述： | ？lanSC310程序員參考手冊(cè) |
| 文件頁(yè)數(shù)： | 35/186頁(yè) |
| 文件大?。?/td> | 918K |
| 代理商： | 20665 |
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1-24
Power Management
system is configured in Maximum ISA mode, it is also possible to use DRQ1 or
DRQ7–DRQ3 as rising-edge wake-up events (bits 0, 2, and 3 of the Activity Mask 1 regis-
ter). If the system is configured in Local-Bus mode, the choice of DRQs is limited to
DRQ1, DRQ2, or DRQ5.
When using IRQ or DRQ pins as wake-up signals, external hardware must hold the active
state (High) until the PMU returns to High-Speed PLL mode. (This is not necessary for
the Ring-Indicate wake-up signals because they are internally latched.) IRQ wake-up
events (IRQ3, IRQ4, and IRQ8) are masked at the PIC and must be enabled in order to
generate a wake-up. However, unlike the IRQs, the DRQ events are not masked at the
DMA controller. Also, for IRQ wake-ups, care must be taken to ensure signal integrity on
the IRQ lines. Glitches on the IRQ lines as small as 4 ns will cause a wake-up to occur.
The PMU has no ability to filter glitches; therefore, the system could be returned to High-
Speed PLL mode by what amounts to a spurious interrupt.
If using multiple DRQs and/or IRQs as wake-up signals, the system designer must
ensure that one wake-up signal does not block the others by being held continuously in
the active state while its corresponding PMU-activity-mask bit is set to 0. These wake-up
sources are logically ORed before edge detection is performed. Wake-ups received dur-
ing Temporary-On SMI or NMI routines (see “Temporary-On Mode” on page 1-26) require
the following special attention:
1. The wake-up is delayed (not serviced by the PMU logic) until the SMI or NMI routine is
completed.
2. The wake-up is serviced and cleared before exiting the SMI or NMI handler when all of
the following conditions are true:
— CPU interrupts are enabled by the routine (to handle other non-wake-up events)
— There is an associated interrupt service routine (ISR) for the wake-up event
— The wake-up is not masked at the PIC
Note that the interrupt handler does not have to explicitly clear the wake-up source. The
CPU just has to acknowledge the active IRQ channel. This results in a lost wake-up event
from the first case. Therefore, if CPU interrupts need to be serviced from within an
SMI/NMI handler, the IRQs that are set up as wake-ups must be masked off at the PIC
(disabled) at the beginning of the SMI/NMI routine, and unmasked (re-enabled) upon exit-
ing the routine. Make sure CPU interrupts are disabled before re-enabling wake-ups at
the PIC.
The ring-in wake-up (RI) persists only until the next refresh. If software tries to clear the
status bits in the Resume Status register prior to that subsequent refresh, the bits may
remain set. Software must clear the Resume Status register on two successive refreshes.
An additional wake-up event is the SUS/RES pin. This event is not maskable by the sys-
tem. For more information, see “Suspend/Resume Pin Logic” on page 1-34.
Figure 1-3 on page 1-20 shows how wake-ups play a part in the power-management flow.
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相關(guān)代理商/技術(shù)參數(shù) |
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| 20-665000-00 | 功能描述:IC 與器件插座 SOWIC TO SOIC ADAPT 20 PINS RoHS:否 制造商:Molex 產(chǎn)品:LGA Sockets 節(jié)距:1.02 mm 排數(shù): 位置/觸點(diǎn)數(shù)量:2011 觸點(diǎn)電鍍:Gold 安裝風(fēng)格:SMD/SMT 端接類(lèi)型:Solder 插座/封裝類(lèi)型:LGA 2011 工作溫度范圍:- 40 C to + 100 C |
| 20-665000-00-P | 制造商:ARIES 制造商全稱(chēng):Aries Electronics, Inc. 功能描述:SOWI-to-SOIC Adapter |
| 206650-1 | 制造商:TE Connectivity 功能描述:206650-1 |
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