
I-20
INDEX
STROBE bit,
3-9
SU bit,
4-56
SU0 bit,
4-59
SU1 bit,
4-59
SU2 bit,
4-43
SU3 bit,
4-58
SU4 bit,
4-58
SUS bit,
4-43
SUS/RES pin. See alsosuspend/resume operation.
overview,
1-2
PMU operating-mode transitions (figure),
1-4
resume input,
1-35
suspend input,
1-35
wake-up events,
1-24
Suspend mode
automatic entry upon Battery Level 4,
1-33
–
1-34
pseudo-Suspend mode,
1-9
purpose and use,
1-7
Suspend to Off Timer Register (Index 87h)
state-transition timing,
1-22
suspend/resume operation,
1-34
–
1-36
avoiding problems,
1-36
programming considerations,
1-35
purpose and use,
1-34
required configuration-register initializations,
1-37
resume input causing SMI,
1-39
resume pseudocode,
1-39
start of SMI handler,
1-37
suspend input causing SMI,
1-37
suspend pseudocode,
1-38
using SMIs,
1-35
SYSCLK signal
disabled in Sleep mode,
1-7
XT-keyboard clock (XTCLK),
B-2
SYSCLK speeds (table),
1-6
System Management Interrupt (SMI). SeeSMIs.
System Timer Registers (table),
3-5
T
T1 bit,
4-52
T2G bit,
3-20
T2OUT bit,
3-20
Temporary-On mode
purpose and use,
1-26
–
1-27
suspend/resume operation,
1-36
TEMT bit,
3-14
TERI bit,
3-15
THRE bit,
3-14
time-base divider-chain bits (table),
3-18
timer registers
Doze to Sleep Timer Register (Index 85h),
1-22
,
4-44
High-Speed to Low-Speed Timer Register (Index
83h),
1-22
,
4-44
Low-Speed to Doze Timer Register (Index 84h),
1-22
,
4-44
Sleep to Suspend Timer Register (Index 86h),
1-22
,
1-37
,
4-44
Suspend to Off Timer Register (Index 87h),
1-22
,
4-45
timer-controlled
shutdown
using
SMI
interface,
1-14
–
1-15
Transmitter Holding Register (Ports 2F8h & 3F8h),
3-11
trigger period select logic (table),
4-52
U
UART registers
converting Port 3FDh from read only to read/write,
4-18
Divisor Latch Lower Byte (Ports 2F8h & 3F8h),
3-12
Divisor Latch Upper Byte (Ports 2F8h & 3F9h),
3-12
Interrupt Enable Register (Ports 2F9h & 3F9h),
3-12
Interrupt Identification Register (Ports 2FAh & 3FAh),
3-12
–
3-13
Line Control Register (Ports 2FBh & 3FBh),
3-13
Line Status Register (Ports 2FDh & 3FDh),
3-14
Modem Control Register (Ports 2FCh & 3FCh),
3-14
Modem Status Register (Ports 2FEh & 3FEh),
3-15
Receiver Buffer Register (Ports 2F8h & 3F8h),
3-11
registers for setting up UART (table),
4-7
Scratch Pad Register (Ports 2FFh & 3FFh),
3-15
Transmitter Holding Register (Ports 2F8h & 3F8h),
3-11
UART Clock Enable Register (Index 92h),
4-49
UART_EN bit,
4-42
UART_IOP bit,
4-42
UART_IR3 bit,
4-42
UART_IR4 bit,
4-42