
Power Management
1-15
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The PMU enters another mode for which the device is programmed to turn off.
It is also important to understand that an expiring SMI device timer clears all four of the
PMC control bits for that device by a short pulse generated when the timer expires. In
addition, the control-register bits for that device are held in reset when the PMU is in
Sleep, Suspend, or Off mode. These conditions only apply to PMC pins that have an SMI
device timer enabled by the SMI Enable register at Index 41h. For more information, see
“Accesses to Powered-Down Device SMI” on page 1-29.
1.2.2
Programmable General-Purpose Pins 2 and 3
Through an option enabled via the General-Purpose I/O 2 and 3 registers at
Indexes 94–95h and the General-Purpose I/O Control register at Index 91h, the
PGP3–PGP2 pins can be enabled to switch from High to Low when the PMU enters Off
mode. This option can be enabled as follows:
I
PGP2
and set bit 7 of the General-Purpose I/O 2 register at Index 94h.
Clear bits 4 and 5 of the General-Purpose I/O Control register at Index 91h,
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PGP3
the General-Purpose I/O 3 register at Index 95h.
Clear bits 6 and 7 of the General-Purpose I/O Control register, and set bit 7 of
This setup causes the PGP pins to default to 1. When the PMU enters Off mode, the
PGP2 or PGP3 pin is driven by the inverse of bit 7 of the General-Purpose I/O 2 register
or the General-Purpose I/O 3 register, respectively. Because the PMU timer delay to Off
mode can be set to as long as 256 min, this feature can be used to turn off a device after
a prolonged period of inactivity.
1.2.3
Latched Power Pin
The Latched Power (LPH) pin can be used to indicate a low battery. The default state of
LPH is 0. When enabled by setting bit 7 of the MMSB Control register at Index 74h, a 0 on
the Battery Level 4 (BL4) input pin causes LPH to drive a 1, provided that the ACIN (AC
Input Active) pin is also 0.