
INDEX
I-3
Clocks. See alsospecific clocks.
clock-switching permutations available with PMU
modes,
1-8
keyboard clock,
B-2
PMU clock speeds (table),
1-6
registers for controlling (table),
4-8
clock-switching logic,
1-16
–
1-18
clock startup and shutdown logic,
1-16
logic flowchart (figure),
1-18
CPU/memory clock switching,
1-16
–
1-17
definition,
1-2
COM bit
Activity Mask 2 Register (Index 76h),
4-41
Activity Status 2 Register (Index A1h),
4-53
Command Delay Register (Index 60h)
8-bit ISA I/O access command delay (table),
4-20
8-bit ISA memory access command delay (table),
4-21
bit descriptions,
4-20
refresh cycle wait states (table),
4-21
ROM BIO wait states (table),
4-21
command delays
duration for various cycles (table),
2-14
purpose and use,
2-14
Configuration Address Register (Port 022h),
4-11
Configuration Data Register (Port 023h),
4-11
configuration index registers
Activity Mask 1 Register (Index 75h),
1-8
,
1-19
,
1-34
,
4-40
–
4-41
Activity Mask 2 Register (Index 76h),
1-8
,
1-19
,
4-41
Activity Status 1 Register (Index A0h),
1-19
,
4-53
Activity Status 2 Register (Index A1h),
1-19
,
4-53
Auto Low-Speed Control Register (Index 9Fh),
4-51
Clock Control Register (Index 8Fh),
4-47
Command Delay Register (Index 60h),
4-20
Control A Register (Index 48h),
4-18
Control B Register (Index 77h),
4-42
controlling low-speed CPU clock,
1-6
CPU Status 0 Register (Index A3h),
4-54
CPU Status 1 Register (Index A4h),
1-9
,
4-55
Doze to Sleep Timer Register (Index 85h),
1-22
,
4-44
Drive Timer Register (Index 47h),
4-17
Function Enable 1 Register (Index B0h),
1-31
,
4-61
–
4-62
Function Enable 2 Register (Index B1h),
2-3
,
4-62
–
4-63
General-Purpose I/O 0 Register (Index 89h),
4-46
General-Purpose I/O 1 Register (Index 9Ch),
4-51
General-Purpose I/O 2 Register (Index 94h),
1-7
,
4-49
General-Purpose I/O 3 Register (Index 95h),
1-7
,
4-49
General-Purpose I/O Control Register (Index 91h),
1-7
,
4-47
–
4-48
High-Speed to Low-Speed Timer Register (Index
83h),
1-22
,
4-44
I/O Activity Address 0 Register (Index 8Ch),
1-8
,
4-46
I/O Activity Address 1 Register (Index 8Dh),
1-8
,
4-46
I/O Timeout Register (Index 40h),
1-31
I/O Wait State Register (Index 61h),
4-22
–
4-23
Low-Speed to Doze Timer Register (Index 84h),
4-44
mandatory settings,
4-2
–
4-4
Memory Configuration 1 Register (Index 66h),
2-3
,
2-4
,
4-28
Memory Configuration 2 Register (Index B9h),
1-7
,
4-69
Memory Write Activity Lower Boundary Register (In-
dex 9Ah),
1-8
,
4-50
Memory Write Activity Upper Boundary Register (In-
dex 9Bh),
1-8
,
4-50
–
4-51
Miscellaneous 1 Register (Index 6Fh),
4-34
–
4-35
Miscellaneous 2 Register (Index 6Bh),
1-27
,
4-30
Miscellaneous 3 Register (Index BAh),
4-70
Miscellaneous 4 Register (Index 44h),
1-29
,
1-41
,
4-15
Miscellaneous 5 Register (Index B3h),
1-28
,
2-15
,
4-65
Miscellaneous 6 Register (Index 70h),
1-34
MMS Address Extension 1 Register (Index 6Ch),
4-31
MMS Address Extension 2 Register (Index 6Eh),
4-33
MMS Address Register (Index 6Dh),
4-31
–
4-33
MMS Memory Wait State 1 Register (Index 62h),
2-4
,
4-23
–
4-24
MMS Memory Wait State 2 Register (Index 50h),
4-19
MMSA Address Extension 1 Register (Index 67h),
4-29
MMSA Device 1 Register (Index 71h),
4-36
MMSA Device 2 Register (Index 72h),
4-37
MMSB Control Register (Index 74h),
1-6
,
1-33
,
4-39
MMSB Device Register (Index 73h),
4-38
MMSB Socket Register (Index A9h),
1-27
,
4-43
NMI/SMI Control Register (Index A5h),
1-26
–
1-29
,
1-32
,
1-33
,
1-36
,
1-38
,
1-39
,
4-56
NMI/SMI Enable Register (Index 82h),
1-32
,
1-33
,
1-37
,
4-43
overview,
4-2
PIO Address Register (Index 45h),
1-29
,
4-15
PIO Timer Register (Index 46h),
1-29
,
4-16
–
4-17
PIRQ Configuration Register (Index B2h),
4-64
PMU Control 1 Register (Index A7h),
1-8
,
1-41
,
4-56
PMU Control 2 Register (Index AFh),
1-22
,
1-32
,
4-61
–
4-62
PMU Control 3 Register (Index ADh),
1-8
,
1-34
,
4-60
PMU operating-mode transitions,
1-8
Power Control 1 Register (Index 80h),
1-6
,
1-9
,
4-42
Power Control 2 Register (Index 81h),
1-7
,
1-9
,
4-43
Power Control 3 Register (Index ABh),
4-58
2-8
,