
I-4
INDEX
Power Control 4 Register (Index ACh),
4-59
recommended settings,
4-4
reference list in alphabetical order (table),
A-1
–
A-2
Reserved Register (Index 6Ah),
4-30
Reserved Register (Index 8Bh),
4-46
Reserved Register (Index 8Eh),
4-46
Reserved Register (Index 90h),
4-47
Reserved Register (Index 93h),
4-49
Reserved Register (Index 9Dh),
4-51
Reserved Register (Index AEh),
4-60
Reserved Registers (Indexes 49–4Fh),
4-18
Reserved Registers (Indexes 52–5Fh),
4-20
Reserved Registers (Indexes 78–7Fh),
4-42
Reserved Registers (Indexes 96–99h),
4-49
Resume Mask Register (Index 08h),
1-19
,
4-11
Resume Status Register (Index 09h),
1-19
,
4-12
ROM Configuration 1 Register (Index 65h),
2-4
,
2-7
,
4-27
ROM Configuration 2 Register (Index 51h),
2-8
,
4-20
ROM Configuration 3 Register (Index B8h),
2-8
,
2-16
,
4-67
–
4-68
Shadow RAM Enable 1 Register (Index 68h),
4-29
Shadow RAM Enable 2 Register (Index 69h),
4-30
Sleep to Suspend Timer Register (Index 86h),
1-22
,
1-37
,
4-44
SMI Enable Register (Index 41h),
1-30
,
1-31
,
4-13
SMI I/O Status Register (Index 42h),
1-30
,
4-14
SMI MMS Page Register (Index AAh),
1-27
,
4-57
SMI Status Register (Index 43h),
1-28
,
4-14
Software Mode Control Register (Index 88h),
1-28
–
1-29
,
4-45
Suspend to Off Timer Register (Index 87h),
1-22
,
4-45
UART Clock Enable Register (Index 92h),
4-49
Version Register (Index 64h),
4-26
Wait State Control Register (Index 63h),
2-4
,
4-25
configuration port registers
Configuration Address Register (Port 022h),
4-11
Configuration Data Register (Port 023h),
4-11
overview,
4-2
configuring élanSC310 microcontroller
clocks (phase-locked loops),
4-8
CPU and PC/AT compatibility (table),
4-5
determining bus configuration (table),
4-5
direct memory accesses (table),
4-6
general-purpose and PMC pins,
4-8
interrupts and their mapping (table),
4-6
memory mapping (MMS windows) (table),
4-6
parallel port (table),
4-7
PC/AT bus and its timing (table),
4-5
power management activities and events (table),
4-9
power management state timers (table),
4-10
power management status (table),
4-9
ROM accesses and ROM cycles (table),
4-10
SMIs and SMI status (table),
4-10
speed of CPU (table),
4-5
system DRAM (table),
4-7
UART (table),
4-7
Control A Register (Index 48h),
4-18
Control B Register (Index 77h),
4-42
CPU and PC/AT compatibility, controlling (table),
4-5
CPU clock, low-speed, controlling,
1-6
CPU speed, controlling (table),
4-5
CPU Status 0 Register (Index A3h)
bit descriptions,
4-54
last PMU mode indicator bits (table),
4-54
Reading status of BL2 pin,
1-32
CPU Status 1 Register (Index A4h)
bit descriptions,
4-55
present PMU mode indicator bits (table),
4-55
reading PMU mode,
1-9
CPU_IDLE bit,
4-30
CPUCLK
High-Speed PLL mode,
1-4
Low-Speed PLL mode,
1-5
PMU clock speeds (table),
1-6
CTS bit,
3-15
D
data-path disabling logic,
1-41
DBUFOE signal,
4-61
DCTS bit,
3-15
DDSR bit,
3-15
device-power-down logic
description,
1-29
–
1-31
SMI device-powerdown flowchart (figure),
1-30
DIR bit
Parallel Control Port (Ports 27Ah & 37Ah),
3-10
Parallel Control Port (Ports 27Ah, 37Ah, & 37Eh),
3-9
direct memory access, controlling (table),
4-6
DISCMD bit,
4-18
DISDEN bit,
4-15
disk drive management registers
Drive Timer Register (Index 47h),
4-17
I/O Wait State Register (Index 61h),
4-22
–
4-23