
Configuration Registers
4-49
4.3.62
UART Clock Enable Register (Index 92h)
This register is used to control the UART clock.
4.3.63
Reserved Register (Index 93h)
This index location is reserved and must be 0.
4.3.64
General-Purpose I/O 2 Register (Index 94h)
This is a write-only register. This register is used to control the PGP2 pin in either power-
management mode or address-decode mode. In power-management mode, the state of
PGP2 is High when the PMU is not in Off mode. When the PMU transitions to Off mode,
the state of PGP2 is determined by bit 7. When bit 7 is 1, PGP2 is Low. When bit 7 is 0,
PGP2 is High. In address-decode mode, PGP2 functions as a simple address decode.
PGP2 is High until the SA9–SA3 signals match bits 6–0 of this register, at which time
PGP2 goes Low for as long as the signals match. PGP2 can also be gated internally with
the I/O Write command signal. The General-Purpose I/O Control register at Index 91h is
used to select how PGP2 operates as an output. PGP2 cannot operate as an input.
4.3.65
General-Purpose I/O 3 Register (Index 95h)
This is a write-only register. This register is used to control the PGP3 pin in either power-
management mode or address-decode mode. In power-management mode, the state of
PGP3 is High when the PMU is not in Off mode. When the PMU transitions to Off mode,
the state of PGP3 is determined by bit 7. When bit 7 is 1, PGP3 is Low. When bit 7 is 0,
PGP3 is High. In address-decode mode, PGP3 functions as a simple address decode.
PGP3 is High until the SA9–SA3 signals match bits 6–0 of this register, at which time
PGP3 goes Low for as long as the signals match. PGP3 can also be gated internally with
the I/O Read command signal. The General-Purpose I/O Control register at Index 91h is
used to select how PGP3 operates as an output. PGP3 cannot operate as an input.
4.3.66
Reserved Registers (Indexes 96–99h)
These index locations are reserved.
7
0
Bit
Default
(Reserved)
0
ENCLK
0
0
0
0
0
0
0
Bit
Name
R/W
Function
7–1
0
W
W
(Reserved)
1 = Enable clock to internal 16450 UART
ENCLK
7
0
Field
Bit
Default
Address Bits 9–3
A7
0
DX
0
A9
0
A8
0
A6
0
A5
0
A4
0
A3
0
7
0
Field
Bit
Default
Address Bits 9–3
A7
0
DX
0
A9
0
A8
0
A6
0
A5
0
A4
0
A3
0