
Power Management
1-41
1.12
OTHER POWER-SAVING FEATURES
The élanSC310 microcontroller has additional features that provide reduced power con-
sumption. These features can be enabled at the system designer’s discretion.
1.12.1
DMA Clock Stop
This feature is enabled by bit 3 of the Function Enable 1 register at Index B0h. It causes
the clock to the 8237 DMA controller to stop except when actually needed to perform a
DMA transfer. This feature operates independently of the PMU mode. If clocks are not
disabled by the PMU, the DMA clock starts after one of the DRQs goes active High, and
the DMA clock continues running until AEN is deasserted.
1.12.2
Data-Path Disabling Logic
The following bits help limit the amount of data-bus toggling in the élanSC310 microcon-
troller to peripheral devices which are not in use:
I
Bits 4 and 5 of the PMU Control 1 register at Index A7h can be set to disable data-bus
toggling to the internal UART and PMU blocks during memory cycles.
I
Bit 4 of the Miscellaneous 4 register at Index 44h, if 1, disables data-bus toggling to
most of the élanSC310 microcontroller (except between the CPU and the external
data-bus interface) during internal DRAM cycles.
Slow Refresh
For systems using DRAM that supports slow refresh, the élanSC310 microcontroller pro-
vides five user-selectable refresh rates. The default refresh rate is the slowest:
8192 refreshes per second. If bits 0 and 1 of PMU Control 1 register at Index A7h are 0,
the refresh rate is controlled by bits 1 and 0 of the Version register at Index 64h. Sup-
ported rates are 32768, 16384, 10922, and 8192 refreshes per second. If bit 0 of the
PMU Control 1 register at Index A7h is 0 and bit 1 is 1, the refresh rate becomes 65536
refreshes per second; if bit 0 is 1, the 8254 becomes the refresh source.
1.12.3
1.12.4
Quiet Bus
Setting bit 2 of the Control A register at Index 48h disables MEMR and MEMW on the ISA
bus from toggling during internal memory cycles.