
1-6
Power Management
Through an option enabled by setting bit 3 of the MMSB Control register at Index 74h, the
PMU can be programmed to periodically start the low-speed CPU clock when the IRQ0
pin (generated by the 8254 timer) is asserted. By default, the clock runs only while IRQ0
is active or the ISR0 bit is High, stopping on the next refresh after this condition is no
longer valid. In this case, the CPU clock runs at 9.2 MHz. The 8259 interrupt controller
must be programmed to unmask IRQ0. By setting bit 0 of the PMU Control 2 register at
Index AFh, the run time may be extended for 64 refresh cycles after ISR0 goes Low.
By setting bit 7 of the Power Control 1 register at Index 80h, the low-speed PLL and video
PLL can be shut down in Doze mode. Shutting down the low-speed PLL also shuts down
the 8254 timer clock, the UART clock, and the keyboard clock; therefore, the IRQ0 wake-
up cannot be used in this instance. The high-speed PLL is always shut down in this mode.
The PMC pins may be programmed to a specific state for this mode. An NMI or SMI may
be generated upon entering Doze mode. The CPUCLK signal runs at 9.2 MHz during the
NMI or SMI handler.
Table 1-1
PMU Clock Speeds
Mode
High-Speed
CPUCLK
Low-Speed
CPUCLK
Video Clock
DMA Clock
SYSCLK
8254 Clock
(Timer)
16450 Clock
(UART)
High-Speed
PLL
33/25/20
MHz
9.2 MHz
14.336 MHz
4.6 MHz
9.2 MHz
1.19 MHz
1.8432 MHz
Low-Speed
PLL
9.2 MHz
4.608/2.304/
1.152/0.56
MHz
14.336 MHz
2.3/1.2/0.58/
0.29 MHz
9.2 MHz
1.19 MHz
1.8432 MHz
Doze
DC
1
DC
1
14.3 MHz/
DC
2
DC
1
9.2 MHz/
DC
2
1.19 MHz/
DC
2
1.8 MHz/DC
2
Sleep
DC
9.2 MHz/
DC
4
14.3 MHz/
DC
2
4.6 MHz/
DC
4
DC
1.19 MHz/
DC
2
1.8 MHz/DC
2
Suspend
DC
9.2 MHz/
DC
4
14.3 MHz/
DC
2
4.6 MHz/
DC
4
DC
1.19 MHz/
DC
2
1.8 MHz/DC
2
Off
DC
9.2 MHz/
DC
4
14.3 MHz/
DC
3
4.6 MHz/
DC
4
DC
1.19 MHz/
DC
3
1.8 MHz/DC
3
Notes:
The DMA clock can be stopped except during DMA transfers. The Function Enable 1 register at Index B0h controls this function.
The CPU clock speed in Low-Speed PLL mode is selectable. For additional information, see “PMU Control 3 Register
(Index ADh)” on page 4-60.
1. Can be programmed to run intermittently (on the IRQ0 pin) at 9.2 MHz.
2. Is a programmable option, but not on a per-clock basis—all clocks with this note are controlled by a single on/off select for
that PMU mode.
3. Is a programmable option—reflects the setting in Suspend mode.
4. Can be programmed to run at 9.2 MHz during temporary-on NMI or SMI handlers.