
1-32
Power Management
1.8
BATTERY-MANAGEMENT LOGIC
The élanSC310 microcontroller’s battery-management logic allows the system designer
to specify up to four battery-detection levels. The four battery-level-indication input pins
are named BL1, BL2, BL3, and BL4. A 0 on one of these inputs indicates a low-battery
condition for that level. Another pin named ACIN, when High, indicates that external non-
battery power has been applied. The following paragraphs give a description of the func-
tionality of each of these pins. Table 1-10 on page 1-32 provides a summary of the
functionality of BL4–BL1.
1.8.1
Battery Level 1
The Battery Level 1 (BL1) pin is intended to be used as a first-line warning, indicating that
battery power is low, but that enough power remains for continued use. The state of this
pin may be read directly at the CPU Status 0 register at Index A3h.
Through an option enabled by bit 5 of the PMU Control 2 register at Index AFh, the CPU
clock in High-Speed PLL mode can be forced to run at 9.2 MHz on all cycles when BL1
and ACIN are Low, thus prolonging battery life.
BL1 may also be programmed to generate SMIs. This feature is enabled by bit 5 of the
NMI/SMI Enable register at Index 82h. This is a level-triggered SMI (i.e., the input should
be held in the trigger state, not pulsed). After system reset, a level change on BL1 from 1
to 0 generates an SMI. During the SMI service routine, the CPU must read the NMI/SMI
Control register at Index A5h to reset the BL1 SMI-generation logic. This read also sets
the logic to look for the opposite state on BL1 to trigger the next SMI. Therefore, any
change of state on BL1 generates an SMI, provided that a read from the NMI/SMI Control
register is always performed in the SMI service routine. Because the NMI/SMI Control
register is also one of the SMI source-polling registers, this read is needed anyway to
determine the SMI source. The SMI handler must also write to the PMU Status 1 register
at Index A2h to clear the PMU SMI request.
An SMI generated by BL1 causes the CPU clock to be started, regardless of the PMU
mode (see “Temporary-On Mode” on page 1-26). The clock remains running until the next
refresh cycle following a write to the NMI/SMI Control register at Index A5h.
1.8.2
Battery Level 2
The Battery Level 2 (BL2) pin is intended to be used as a second-line warning in a four-
level battery-management system, or as a final warning in a two-level system. The state
of this pin may be read directly at the CPU Status 0 register at Index A3h.
Table 1-10
Battery-Level Management Functionality
Pin
Slow Clock
Level SMI
Edge SMI
Force to Sleep
Force to Suspend
BL1
I
I
BL2
I
I
BL3
I
BL4
I