
3-8
PC/AT Peripheral Registers
3.2.5
Parallel Port Interface Registers
The parallel port is register-compatible with the industry-standard, AT-compatible, EPP-
compliant parallel port. The parallel port can be set up to have a base I/O address of
3BCh, 278h, or 378h. EPP support is only possible when the base I/O address is set to
278h or 378h. EPP-mode enable and bidirectional enable/control are set by bits 2–0 of
the Function Enable 1 register at Index B0h. The parallel port interrupt is fixed at IRQ7.
The base I/O address is set using bits 1–0 of the Parallel Port Address Select Register
(Port 3D4h, Index 20h).The setting of the parallel port base I/O address can only be done
during the processor initialization sequence. Refer to Section 3.1.2, "Bus Initialization
Register (Port 3D4h, Index 19h)," on page 3-2 and to Table 4-2, "Mandatory Configura-
tion Bit Settings," on page 4-3 for details on this initialization sequence.
After the parallel port I/O address has been set and, optionally, the EPP support or bidi-
rectional support has been enabled, then the parallel port registers may be accessed as
I/O ports. The parallel port register fields are different for AT-compatible mode vs. EPP-
compliant mode. Section 3.2.5.1, "AT-Compatible Mode," describes the parallel port reg-
isters when the parallel port is configured for AT-compatible mode. Section 3.2.5.2, "EPP-
Compliant Mode," describes the parallel port registers when the parallel port is config-
ured for EPP-compliant mode.
Table 3-9
DMA Page Registers
Address
R/W
Description
0080h
R/W
General Register
0081h
R/W
Channel 2 Page Register
0082h
R/W
Channel 3 Page Register
0083h
R/W
Channel 1 Page Register
0084h
R/W
General Register
0085h
R/W
General Register
0086h
R/W
General Register
0087h
R/W
Channel 0 Page Register
0088h
R/W
General Register
0089h
R/W
Channel 6 Page Register
008Ah
R/W
Channel 7 Page Register
008Bh
R/W
Channel 5 Page Register
008Ch
R/W
General Register
008Dh
R/W
General Register
008Eh
R/W
General Register
008Fh
R/W
General Register