
1-26
Power Management
1.7.1
Temporary-On Mode
Only the first three SMI or NMI sources listed above will cause the CPU, DMA, and inter-
nal system clocks to start if they were stopped. If not in the High-Speed PLL or Low-
Speed PLL mode, the clocks will run based on the 9.2-MHz frequency until the next
refresh after an I/O write to the NMI/SMI Control register at Index A5h is performed. This
is called Temporary-On mode.
This mode is useful when it is desired to have the CPU perform certain tasks before
changing PMU modes, or when the CPU receives a low-battery indication or a resume
keystroke, regardless of whether it is asleep or awake. For the first two sources, when in
Temporary-On mode, the PMU remains in the same state it was in before the CPU clock
started. It does not change to High-Speed PLL mode. For the third source, the PMU
makes a transition to High-Speed PLL mode before the SMI is generated. Writing to the
NMI/SMI Control register causes the PMU to leave Temporary-On mode and return to
Figure 1-4
SMI Processing Flowchart
Exit SMI or NMI handler
Mode-change SMI or NMI from
Figure 1-3
SMI or NMI enabled for
requesting device/event
Miscellaneous SMI or NMI
sources
Battery low
(BL1,BL2, or BL3)
I/O cycle attempted to power
off peripheral
Timer interrupt
(IRQ0)
Generate SMI/NMI (PMU starts CPUCLK if source was
mode change, BL1, BL3, or Resume keystroke)
SMI or NMI routine flow:
1. Determine source of SMI or NMI (read registers A5h, 43h, and B3h).
2. Clear SMI or NMI request (write Index A2h, 43h, B3h, or address of external device).
3. Perform tasks.
SMI or NMI routine flow:
Read A5h again.
Any additional bits set
SMI or NMI routine flow:
Was SMI or NMI source the Resume
key, BL3–BL1, or mode change
Yes
SMI or NMI routine flow:
Write to register A5h to
enable mode change
No
No
Yes