
Configuration Registers
4-43
4.3.46
Power Control 2 Register (Index 81h)
This register activates the PMC2 output pin in Sleep, Suspend, and Off modes. It also
enables/disables the low-speed PLL and video PLL in Sleep, Suspend, and Off modes.
4.3.47
NMI/SMI Enable Register (Index 82h)
This register is used to enable the generation of NMIs or SMIs during certain conditions,
such as mode changes or battery-low conditions. By default, NMIs and SMIs are dis-
abled. The choice of SMIs or NMIs is selected by bit 7 of the SMI MMS Upper Page regis-
ter at Index A9h.
7
0
Bit
Default
0CLK_SUS
0
SU2
0
0CLK_SLP
0
SP2
0
0
0
0
0
Bit
Name
R/W
Function
7
0CLK_SUS
R/W
1 = Low-speed PLL and Video PLL are shut down in Suspend and Off
modes
1 = State of PMC2 pin in Suspend and Off modes
(Reserved)
1 = Low-speed PLL and video PLL are shut down in Sleep mode
1 = State of PMC2 pin in Sleep mode
(Reserved)
6
5–4
3
2
1–0
Note:
The state of PMC2 after power-on is Low. When the bit is 0, the corresponding PMC output is Low. For details,
see Chapter 1, “Power Management.”
SU2
R/W
R/W
R/W
R/W
R/W
0CLK_SLP
SP2
7
0
Bit
Default
BL3
0
BL2
0
BL1
0
SUS
0
SLP
0
DZ
0
ON
0
RESU
0
Bit
Name
R/W
Function
7
6
5
4
3
2
1
BL3
BL2
BL1
SUS
SLP
DZ
ON
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 = Battery low warning 3 generates an NMI or SMI
1 = Battery low warning 2 generates an NMI or SMI
1 = Battery low warning 1 generates an NMI or SMI
1 = PMU generates NMI or SMI before entering Off mode from Suspend mode
1 = PMU generates NMI or SMI before entering Suspend mode from Sleep mode
1 = PMU generates NMI or SMI before entering Sleep mode from Doze mode
1 = PMU generates NMI or SMI before entering Doze mode from Low-Speed PLL
mode
1 = SUS/RES pin will generate NMI or SMI
0
Note:
Bit 7 of AT-compatible port 70h must be 0 for NMIs to occur.
RESU
R/W