
I-2
INDEX
AF bit,
3-19
AIE bit,
3-19
ALTA20 bit,
3-21
Am386SXLV microprocessor, integration in élanSC310
microcontroller,
xi
AT Peripheral Registers.
ters.
See
PC/AT Peripheral Regis-
AUTLOW bit,
4-42
Auto Low-Speed Control Register (Index 9Fh)
bit descriptions,
4-52
low-speed duration period select logic (table),
trigger period select logic (table),
4-52
4-52
Auto Low-Speed Logic
overview,
purpose and use,
1-3
1-40
AUTOFDX bit,
3-9
B
battery-management logic,
AC Input Status (ACIN) pin,
Battery Level 1 (BL1) pin,
Battery Level 2 (BL2) pin,
Battery Level 3 (BL3) pin,
Battery Level 4 (BL4) pin,
functionality of BL4–BL1 (table),
overview,
1-2
1-32
–
1-34
1-34
1-32
1-32
1-33
1-33
–
1-33
–
1-34
1-32
BHE bit,
4-14
BI bit,
3-14
BKMISS bit
Dram bank miss wait state select logic (table),
function,
4-25
4-25
BL1 bit
NMI/SMI Enable Register (Index 82h),
4-43
BL1 pin,
1-32
BL1IN bit,
4-54
BL1LOWSP bit,
4-61
BL2 bit
NMI/SMI Enable Register (Index 82h),
4-43
BL2 pin
battery-management logic,
SMI generation,
1-32
–
1-34
1-33
BL2IN bit,
4-54
BL3 bit
NMI/SMI Enable Register (Index 82h),
4-43
BL3 pin,
1-33
BL3IN bit,
4-54
BL4 pin,
1-33
–
1-34
bus
bus option status table,
4-28
determining bus configuration (table),
4-5
general bus I/O wait states (table),
4-23
PC/AT bus,
4-5
quiet bus feature,
1-41
bus configurations,
2-5
–
2-6
élanSC310 microcontroller bus configurations (fig-
ure),
2-5
ISA and local bus configurations,
2-5
pins for bus configuration (table),
2-5
supported by élanSC310 microcontroller,
2-2
BUSY bit
Parallel Status Port (Ports 279h & 379h),
3-10
Parallel Status Port (Ports 279h, 379h & 3BDh),
3-9
C
CAS0H signal
selecting DRAM memory banks,
2-3
CAS0L signal
selecting DRAM memory banks,
2-3
CAS1L signal
selecting DRAM memory banks,
2-3
central processing unit. SeeCPU.
CFG0 bit
bus option status table,
4-28
function,
4-28
CFG1 bit
bus option status table,
4-28
function,
4-28
CHGFUSET bit,
4-61
CHGON bit,
4-61
Clock Control Register (Index 8Fh)
bit descriptions,
4-47
PLL restart time select logic (table),
4-47
clock sources, PMU,
1-9