
INDEX
I-21
UF bit,
3-19
UIE bit,
3-19
UIP bit,
3-17
V
VD bit
Activity Mask 2 Register (Index 76h),
4-41
Activity Status 2 Register (Index A1h),
4-53
Version Register (Index 64h)
bit descriptions,
4-26
read functions (table),
4-26
read version stepping level decode (table),
4-26
refresh interval select logic (table),
4-27
write functions (table),
4-26
video clock speeds (table),
1-6
Video PLL,
1-8
VRT bit,
3-19
W
wait state registers
I/O Wait State Register (Index 61h)
bit descriptions,
4-22
floppy disk drive wait states (table),
4-22
general bus I/O wait states (table),
4-23
hard drive wait states (table),
4-23
MMS Memory Wait State 1 Register (Index 62h)
16-bit ISA memory-cycle wait states (table),
4-24
8-bit ISA memory-cycle wait states (table),
4-24
bit descriptions,
4-23
setting up Page-mode DRAM accesses,
2-4
MMS Memory Wait State 2 Register (Index 50h)
bit descriptions,
4-19
ROM DOS command delay select logic (table),
4-19
ROM DOS wait state select logic (table),
4-19
Wait State Control Register (Index 63h)
bit descriptions,
4-25
DRAM bank miss wait state select logic (table),
4-25
DRAM first cycle wait state select logic (table),
4-25
setting up Page-mode DRAM accesses,
2-4
wait states and command delays
33-MHz wait states (table),
2-5
command delay duration for various cycles (table),
2-14
Enhanced Page mode,
2-4
memory-speed initialization example (table),
2-4
Page-mode DRAMs,
2-4
ROM-BIOS, ROM-DOS, and ISA cycles,
2-14
wait states for various cycles (table),
2-15
wake-up logic
definition,
1-2
events allowed,
1-23
–
1-24
IRQ or DRQ pins,
1-24
ring-in wake-ups,
1-24
Temporary-ON SMI or NMI routine requirements,
1-24
wake-up signal descriptions (table),
1-23
wake-up logic,
1-23
–
1-24
WLB0 bit,
3-13
WLB1 bit,
3-13
X
X1SEL bit,
4-61
XT Keyboard Data Register (Port 060h),
3-20
XTALUSE bit,
4-62
XTCLK,
B-2
XTKBDEN bit,
4-60
XT-keyboard interface
block diagram,
B-1
controlling,
B-2
enabled by bit 3 of Index 0ADh,
B-2
I/O map summary,
B-2
keyboard data port,
B-2
overview,
B-1
pins used,
B-2
timing,
B-3