參數(shù)資料
型號: 20665
英文描述: ?lanSC310 Programmer's Reference Manual
中文描述: ?lanSC310程序員參考手冊
文件頁數(shù): 48/186頁
文件大小: 918K
代理商: 20665
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Power Management
1-37
1.9.1
Required Initialization
For the following SUS/RES SMI-handler design to work, the following configuration-regis-
ter initializations must be performed:
I
Initialize the Sleep-to-Suspend time-out to a nonzero value, such as writing 01h to the
Sleep to Suspend Timer register at Index 86h.
I
Allow the resume input to generate an SMI. This is done via bit 0 of the NMI/SMI
Enable register at Index 82h.
I
Set bit 7 of the SMI MMS Upper Page register at Index A9h to select an SMI instead of
an NMI. This choice applies to all PMU events that are unmasked via the NMI/SMI
Enable register at Index 82h.
I
Set up the SMM memory area to the desired system memory location (bits 5–4 of the
SMI MMS Upper Page register at Index A9h and the SMI MMS Page register at
Index AAh).
I
Mask all wake-up events (via the Resume Mask register at Index 08h) and activities
that can cause the system to wake up (bits 6 and 4–0 of the Activity Mask 1 register at
Index 75h). This means only the resume input can wake up the system from Sleep or
Suspend modes, ensuring the resume SMI is always executed.
Start of SMI Handler
SMI handler code must determine why the handler has been entered. Since all SMIs
cause the processor to enter Real mode and jump to the reset vector, it must be deter-
mined early in the boot code whether an SMI handler is being executed (bit 7 of the Ver-
sion register at Index 64h). If so, the handler must determine whether a suspend or a
resume is in progress. This may be accomplished by reading the NMI/SMI Control regis-
ter at Index A5h and checking to see whether the SMI was caused by a Sleep-to-Sus-
pend mode transition (bit 3) or by a resume input (bit 0).
1.9.2
1.9.3
Suspend Input Caused the SMI
If a suspend input caused the SMI, the following events occurred:
1. The system was running in High-Speed PLL, Low-Speed PLL, or Doze mode.
2. A rising edge was detected on the SUS/RES input (a suspend input).
3. The PMU started to ignore further activity on the SUS/RES input (SUS/RES activity).
4. The PMU stepped down through the PMU modes, one per refresh, until Sleep mode
was entered. (Note that the PMU would wake up to High-Speed PLL mode if a resume
input had occurred at this point.)
5. The Sleep-to-Suspend timer expired.
6. The PMU mode started to change from Sleep to Suspend, causing an SMI. At the
same time, the PMU became capable of buffering (delaying) one subsequent
SUS/RES activity. (If this activity occurred at this point, it would be delayed until
Index A5h was next written. The PMU would then process the activity as if it had just
occurred.) In addition, the PMU entered Temporary-On mode, causing the CPU to
start running at 9.2 MHz.
7. When the SMI handler was entered, SMIs were automatically masked by the CPU
until the next execution of the RES3 instruction.
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