
Configuration Registers
4-39
4.3.40
MMSB Control Register (Index 74h)
This register controls MCU and PMU functions.
Bit 7
If bit 7 = 0 and ACIN = 0, the PMU transitions to Suspend mode when BL4 = 0.
Bit 6
bit has no effect on whether an SMI for BL2 is generated. It also does not have an effect
on the status read at the CPU Status 0 register at Index A3h.
If bit 6 = 0 and ACIN = 0, the PMU transitions to Sleep mode when BL2 = 0. This
Bit 1
registers and address extension registers for pages 0–3, this bit selects either the MMSA
or the MMSB for programming. In other words, this bit directs the I/O address to either the
MMSA or the MMSB. If this bit is 1, an I/O cycle accesses the MMSA; otherwise, an I/O
cycle accesses the MMSB.
Because the MMSA and the MMSB use the same I/O address for the page
Bit 0
disabled. If this bit is 1, each window can be individually enabled/disabled via bit 7 of the
appropriate page register.
This bit enables/disables all windows in the MMSB. If this bit is 0, all windows are
7
0
Bit
Default
NENLB4
0
NENLB2
0
(Reserved)
ENPMCIRQ0
0
PGP1DIR
0
MMSABSEL
0
ENMMSB
0
0
0
Bit
Name
R/W
Function
7
NENLB4
R/W
1 = BL4 going active does not cause the PMU to transition to Suspend
mode.
1 = BL2 going active does not cause the PMU to transition to Sleep mode.
(Reserved—must be 0)
(Reserved—must be 0)
Enable IRQ0 active in Doze mode:
1 = Enabled.
If this bit is 1 and bit 0 of the PMU Control 2 register at Index AFh is 0, the
CPUCLK signal is active while IRQ0 is High in Doze mode. If this bit is 1
and bit 0 of the PMU Control 2 register is 1, the CPUCLK signal remains
active for an additional 64 refresh cycles after IRQ0 is deasserted.
PGP1 pin direction:
0 = Input
1 = Output
MMSA and MMSB select bit:
0 = MMSB
1 = MMSA
Enable MMSB:
1 = Enabled
6
5
4
3
NENLB2
R/W
R/W
R/W
R/W
ENPMCIRQ0
2
PGP1DIR
R/W
1
MMSABSEL
R/W
0
ENMMSB
R/W