
4-40
Configuration Registers
4.3.41
Activity Mask 1 Register (Index 75h)
This register is used in conjunction with the Activity Mask 2 register at Index 76h and the
Resume Mask register at Index 08h to enable which activities are detected by the PMU.
Each of these bits masks out the corresponding activity. A 1 means the activity is
masked; a 0 means it is counted. For information on status and enabling ACIN activity,
see “Activity Status 1 Register (Index A0h)” on page 4-53 and “PMU Control 3 Register
(Index ADh)” on page 4-60.
Bit 7
causes a PMU transition from either Low-Speed PLL or Doze mode to High-Speed PLL
mode. This bit does not allow the above stated IRQ levels to wake up the processor from
Sleep, Suspend, or Off mode.
INT means that all interrupts from IRQ2 to IRQ15 can serve as PMU activity that
IRQ3, IRQ4, and IRQ8 can be programmed individually by the Resume Mask register at
Index 08h to act as wake-up events. Unmasking these events allows their occurrence to
wake up the system from Sleep, Suspend, or Off mode into High-Speed PLL mode.
Bit 6
going active to count as activity.
Bit 4 of the PMU Control 3 register at Index ADh must also be set to permit ACIN
7
0
Bit
Default
INT
0
ACIN
0
MMS
0
KB
0
DRQ3
0
DRQ2
0
DRQ1
0
DRQ7–DRQ5
0
Bit
Name
R/W
Function
7
INT
R/W
Interrupt recognition:
1 = Disabled
0 = Enabled
AC adapter input or Low-to-High transition of bit 5 of the Miscellaneous 6
register at Index 70h recognition:
1 = Disabled
0 = Enabled
MMS cycle activity recognition:
1 = Disabled
0 = Enabled
Keyboard interrupt (IRQ1) activity recognition:
1 = Disabled
0 = Enabled
DRQ3 activity recognition:
1 = Disabled
0 = Enabled
DRQ2 activity recognition:
1 = Disabled
0 = Enabled
DRQ1 activity recognition:
1 = Disabled
0 = Enabled
DRQ7–DRQ5 activity recognition:
1 = Disabled
0 = Enabled
6
ACIN
R/W
5
MMS
R/W
4
KB
R/W
3
DRQ3
R/W
2
DRQ2
R/W
1
DRQ1
R/W
0
DRQ7–DRQ5
R/W
Note:
Activities are not detected during the execution of SMIs or NMIs.