
INDEX
I-13
ON bit
NMI/SMI Control Register (Index A5h),
4-56
NMI/SMI Enable Register (Index 82h),
4-43
ONCLK0 bit,
4-60
ONCLK1 bit,
4-60
operating-mode transitions, PMU
High-Speed PLL,
1-8
illustration,
1-4
Low-Speed PLL,
1-8
registers for setting activities,
1-8
Video PLL,
1-8
OUT1 bit,
3-14
OUT2 bit,
3-14
output drive strength select logic (table),
4-69
P
page 0-3 device select (table)
MMSA Device 1 Register (Index 71h),
4-36
MMSB Device Register (Index 73h),
4-38
page 4-7 device select (table),
4-37
page mode
Enhanced Page mode,
2-4
Page-mode DRAMs,
2-4
page register
contents description (table),
4-32
MMSA/B page register I/O addresses (table),
4-32
pages
definition,
2-4
page hits,
2-4
parallel port
registers for setting up (table),
4-7
Parallel Port Interface Registers,
3-8
–
3-11
AT-compatible mode
Parallel Control Port (Ports 27Ah, 37Ah, & 37Eh),
3-9
Parallel Data Port (Ports 278h, 378h, & 3BCh),
3-9
Parallel Status Port (Ports 279h, 379h & 3BDh),
3-9
EPP-compliant mode
Parallel Control Port (Ports 27Ah & 37Ah),
3-10
Parallel Data Port (Ports 278h & 378h),
3-10
Parallel EPP 32-Bit Data Register (Ports 27C-27Fh
& 37C-37Fh),
3-11
Parallel EPP Address Port (Ports 27Bh & 37Bh),
3-11
Parallel Status Port (Ports 279h & 379h),
3-10
overview,
3-8
–
3-11
PC/AT bus. See also bus.
controlling PC/AT bus and its timing (table),
4-5
determining bus configuration (table),
4-5
PC/AT compatibility with CPU, controlling (table),
4-5
PC/AT peripheral registers
conflicts with mirrored I/O registers (note),
3-1
DMA Controller Registers
DMA Controller 1 addresses (table),
3-5
DMA Controller 2 addresses (table),
3-7
DMA Page Registers,
3-7
–
3-8
Interrupt Controller Registers
Interrupt Controller 1 I/O addresses (table),
3-3
Interrupt Controller 2 I/O addresses (table),
3-4
NMI/RTC Index Address Register (Port 070h),
3-21
overview,
3-1
Parallel Port Interface Registers,
3-8
–
3-11
AT-compatible mode
Parallel Control Port (Ports 27Ah, 37Ah, &
37Eh),
3-9
Parallel Data Port (Ports 278h, 378h, & 3BCh),
3-9
Parallel Status Port (Ports 279h, 379h & 3BDh),
3-9
EPP-compliant mode
Parallel Control Port (Ports 27Ah & 37Ah),
3-10
Parallel Data Port (Ports 278h & 378h),
3-10
Parallel EPP 32-Bit Data Register (Ports
27C-27Fh & 37C-37Fh),
3-11
Parallel EPP Address Port (Ports 27Bh &
37Bh),
3-11
Parallel Status Port (Ports 279h & 379h),
3-10
overview,
3-8
–
3-11
UART registers
Divisor Latch Lower Byte (Ports 2F8h & 3F8h,
3-12
Divisor Latch Upper Byte (Ports 2F8h & 3F9h),
3-12
Interrupt Enable Register (Ports 2F9h & 3F9h),
3-12
Interrupt Identification Register (Ports 2FAh &
3FAh),
3-12
–
3-13
Line Control Register (Ports 2FBh & 3FBh),
3-13
Line Status Register (Ports 2FDh & 3FDh),
3-14
Modem Control Register (Ports 2FCh & 3FCh),
3-14
Modem Status Register (Ports 2FEh & 3FEh),
3-15
Receiver Buffer Register (Ports 2F8h & 3F8h),
3-11
Scratch Pad Register (Ports 2FFh & 3FFh),
3-15
Transmitter Holding Register (Ports 2F8h &
3F8h),
3-11
XT Keyboard Data Register (Port 060h),
3-20