
2-4
Memory Management
The élanSC310 microcontroller also supports a variety of speeds of ROM. Some speeds
require wait states to be inserted in memory accesses between the point in a cycle when
the read or write signal is asserted and the point where the data is transferred to or from
the memory device. The number of wait states to be inserted under different conditions is
under programmer control.
Page-mode DRAMs are organized so that successive locations are along the same row,
or
page
. This allows the memory controller to generate a single-row address if successive
accesses happen to lie in the same page (a
page hit
ory cycle can be shortened by eliminating the row-address portion of the cycle. At the
programmer’s discretion, wait states may be inserted into the Page-mode cycle. The pro-
grammer has the option to set the number of wait states after a page miss and the num-
ber of first-cycle wait states. The number of wait states for a page-hit read cycle and a
page-hit write cycle are fixed at 0 and 1, respectively.
). When a page hit occurs, the mem-
The settings in Table 2-3 on page 2-4 set up Page-mode DRAM accesses using the MOD
select bit of the Memory Configuration 1 register at Index 66h. They set the first-cycle wait
state to 3 cycles (the default) and the bank-miss wait states to 5 by setting the following
bits:
I
Bits 5 and 6 of the Wait State Control register at Index 63h
I
Bit 5 of the ROM Configuration 1 register at Index 65h
I
Bit 4 of the MMS Memory Wait State 1 register at Index 62h
The élanSC310 microcontroller also supports Enhanced Page mode when both banks of
DRAM are used. It may be selected using bit 0 of the Memory Configuration 1 register at
Index 66h. This mode effectively doubles the page size by arranging the DRAM address
lines such that one page is spread across both DRAM banks. This avoids the precharge
penalty that would otherwise occur when incrementing across the bank-section boundary.
For more information on the Enhanced-Page-mode address translation, see the
élanSC310 Microcontroller Data Sheet,
PID 20668
.
Table 2-3
Memory-Speed Initialization Example
Instruction
Ports
Data
Comment
IOW
IOW
022h
023h
66h
xxxx xx10
Set memory mode to Page-mode DRAMs. Note that bits 7–5 of
this register are read only because they affect the choice of
bus.
IOW
IOW
022h
023h
63h
x11x xxxx
Set top bits of first-cycle wait state to 3 and bank-miss wait
state to 5.
IOW
IOW
022h
023h
65h
xx1x xxxx
Set low bit of first-cycle wait to 3.
IOW
IOW
022h
023h
62h
xxx1 xxxx
Set low bit of bank-miss waits to 5.