
4-10
Configuration Registers
4.1.3.15
To Control the Power Management State Timers
4.1.3.16
To Map ROM Accesses and Control ROM Cycles
4.1.3.17
To Control SMIs and Determine Status
See
And program bits
“High-Speed to Low-Speed Timer Register (Index 83h)” on page 4-44
7–0
“Low-Speed to Doze Timer Register (Index 84h)” on page 4-44
7–0
“Doze to Sleep Timer Register (Index 85h)” on page 4-44
7–0
“Sleep to Suspend Timer Register (Index 86h)” on page 4-44
7–0
“Suspend to Off Timer Register (Index 87h)” on page 4-45
7–0
“PMU Control 2 Register (Index AFh)” on page 4-61
7–6
See
And program bits
“MMS Memory Wait State 2 Register (Index 50h)” on page 4-19
6 and 2–0
“ROM Configuration 2 Register (Index 51h)” on page 4-20
1–0
“Command Delay Register (Index 60h)” on page 4-20
7 and 4
“MMS Memory Wait State 1 Register (Index 62h)” on page 4-23
6–5
“ROM Configuration 1 Register (Index 65h)” on page 4-27
3–0
“Miscellaneous 5 Register (Index B3h)” on page 4-65
6–4 and 2
“ROM Configuration 3 Register (Index B8h)” on page 4-67
7–0
See
And program bits
“I/O Timeout Register (Index 40h)” on page 4-12
2–0
“SMI Enable Register (Index 41h)” on page 4-13
4–0
“SMI I/O Status Register (Index 42h)” on page 4-14
3–0
“SMI Status Register (Index 43h)” on page 4-14
6–0
“Wait State Control Register (Index 63h)” on page 4-25
7
“Version Register (Index 64h)” on page 4-26
7
“Miscellaneous 2 Register (Index 6Bh)” on page 4-30
0
“NMI/SMI Enable Register (Index 82h)” on page 4-43
7–0
“PMU Status 1 Register (Index A2h)” on page 4-54
7–0
“NMI/SMI Control Register (Index A5h)” on page 4-56
7–0
“SMI MMS Upper Page Register (Index A9h)” on page 4-57
7–4
“SMI MMS Page Register (Index AAh)” on page 4-57
7–0
“PMU Control 3 Register (Index ADh)” on page 4-60
6
“Function Enable 1 Register (Index B0h)” on page 4-61
5–4
“Miscellaneous 5 Register (Index B3h)” on page 4-65
1–0