
1-22
Power Management
1.5
STATE-TRANSITION TIMER
The state-transition-timer logic allows the system designer to specify the amount of time
that the PMU waits between state transitions when no activity is occurring. As shown in
Table 1-3 on page 1-11, the time values are programmed through the Mode Timer regis-
ters at Indexes 83–87h.
The High-Speed to Low-Speed Timer register at Index 83h is used in High-Speed PLL
mode. By default, it is programmed in increments of 1512 s, with a minimum time of
1512 s when set to a value of 1 and a maximum time of 498 ms (1512 255) when pro-
grammed to FFh. If bit 6 of the PMU Control 2 register at Index AFh is 1, the time incre-
ments for this register change to 116 s, for a minimum time of 116 s and a maximum
time of 15.94 s. When this time expires, the PMU changes to Low-Speed PLL mode.
The Low-Speed to Doze Timer register at Index 84h is used in Low-Speed PLL mode. By
default, it is programmed in increments of 116 s, with a minimum time of 116 s when set
to a value of 1 and a maximum time of 15.94 s when programmed to FFh. If bit 7 of the
PMU Control 2 register at Index AFh is 1, the time increments for this register change to
14 s, for a minimum time of 14 s and a maximum time of 63.75 s. When this time expires,
the PMU changes to Doze mode.
The Doze to Sleep Timer register at Index 85h is used in Doze mode. It is always pro-
grammed in 4-s increments, with a minimum time of 4 s and a maximum time of 1020 s
(4 255). When this time expires, the PMU changes to Sleep mode.
The Sleep to Suspend Timer register at Index 86h is used in Sleep mode. It is always pro-
grammed in 116-s increments, with a minimum time of 116 s and a maximum time of
15.94 s (116 255). When this time expires, the PMU changes to Suspend mode.
The Suspend to Off Timer register at Index 87h is used in Suspend mode. It is always
programmed in 64-s increments, with a minimum time of 64 s and a maximum time of
16320 s (64 255), equivalent to 4 hr and 32 min. When this time expires, the PMU
changes to Off mode. Since Off mode is the last state, there is no timer for it.
The State Transition Timer, also known as the PMU Timer, is an internal timer whose
value cannot be read by the system. This timer counts up from 0 and is compared to the
Transition Timer register associated with the current PMU mode. When the PMU Timer
exceeds the time programmed into the appropriate Mode Timer register, the mode
change is initiated and the PMU Timer is reset to 0.
When one of the above registers is cleared, upon reaching the PMU mode corresponding
to that register, the PMU timer will reset and stop counting. The PMU will thus remain in
that mode unless an activity is detected or the PMU is forced into another state via the
SUS/RES pin, BL2 or BL4 pin, or a write to the Software Mode Control register at
Index 88h. Thus, for example, if the High-Speed to Low-Speed Timer register at
Index 83h is cleared, the PMU never leaves High-Speed PLL mode unless one of the pre-
viously mentioned events occurs.