參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 96/166頁
文件大小: 1145K
代理商: ARM966E-S
7-2
System Controller
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
When the core performs a nonbufferable write that misses the on-chip
memory as indicated by the address decoders, the System Controller
must stall the core until the Write Buffer is empty and maintain the stall
until the access to the AHB is complete.
7.2 Clock Control
When accessing the AHB bus for accesses that do not use the Write
Buffer, the internal clock enable CLKEN must include the effects of
HCLKEN, HREADY, and HGRANT to ensure that the core is
synchronized to the AHB bus. The AHB BIU must inform the System
Controller when each transfer has completed. The System Controller
determines when an external access is being performed and qualifies the
internal clock enables with HCLKEN from the AHB interface. Using
HCLKEN effectively slows down the operation of the ARM966E-S to the
AHB bus frequency.
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