參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 125/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
Breakpoints, Watchpoints, and External Debug Requests
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
10-9
10.4.1 Entry into Debug State on Breakpoint
Any instruction being fetched from memory is sampled at the end of a
cycle. To apply a breakpoint to that instruction, the breakpoint signal
must be asserted by the end of the same cycle as shown in Figure 10.4.
You can build external logic, such as additional breakpoint comparators,
to extend the breakpoint functionality of the EmbeddedICE-RT logic.
These outputs must be applied to the DBGIEBKPT input. This signal is
ORed with the internally generated breakpoint signal before being
applied to the ARM9E-S core control logic. The timing of the input makes
it unlikely that data-dependent external breakpoints are possible.
A breakpointed instruction is allowed to enter the Execute stage of the
pipeline, but any state change as a result of the instruction is prevented.
All writes from previous instructions complete as usual.
The Decode cycle of the debug entry sequence occurs during the
Execute cycle of the breakpointed instruction. The latched breakpoint
signal forces the processor to start the debug sequence.
Figure 10.4 shows the breakpoint timing.
Table 10.3
Debug State Figure Notations
Term
Definition
Fx, Dx, Ex, Mx, Wx
Fetch, Decode, Execute, Memory, and Writeback
stages for instruction x on INSTR[31:0]
Ddebug
Decode debug entry
Edebug1, Edebug2
Execute debug entry
ldr
Load register from memory instruction
Dp
Data processing instruction
B
Branch instruction
T
Trigger instruction
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