參數(shù)資料
型號(hào)： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊(cè)6月1日
文件頁數(shù)： 84/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
5-14
AHB Interface Unit
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
Figure 5.5
Transfer with Wait States
When a transfer is extended with wait states, it ends up extending the
address phase of the next transfer. Figure 5.6 shows three transfers to
unrelated addresses: A, B, and C. The transfers to addresses A and C
both have zero wait states, but the transfer to address B has one wait
state. Extending the data phase of the transfer to address B extends the
address phase of the transfer to address C.
Figure 5.6
Multiple Transfers
A
CLK
HADDR[31:0]
Control
HWDATA[31:0]
HREADY
HRDATA[31:0]
Control
Data (A)
(A)
Address
Phase
Data Phase
A
CLK
HADDR[31:0]
Control
HWDATA[31:0]
HREADY
HRDATA[31:0]
Data
(A)
B
C
Control (A)
Control (C)
Data
(B)
Control (B)
Data (B)
Data (C)
Data (A)
(C)
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