參數(shù)資料
型號(hào)： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊(cè)6月1日
文件頁數(shù)： 12/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
xii
Contents
Rev. A
Copyright 1999–2001 by LSI Logic Corporation. All rights reserved.
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
Typical Debug System
ARM9E-S Processor and Debug Logic
Clock Synchronization Logic
Breakpoint Timing
Watchpoint Entry with Data Processing Instruction
Watchpoint Entry with Branch
The ARM9E-S, TAP Controller, and EmbeddedICE-RT
Debug Communications Channel Status Register
Coprocessor 14 Debug Status Register Format
10-2
10-3
10-6
10-10
10-11
10-12
10-15
10-17
10-18
Tables
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.1
4.2
5.1
5.2
5.3
5.4
5.5
5.6
10.1
10.2
Supported Data Types
ARM9E-S Processor Modes
Instruction Format Field Descriptions
Mode Bits
CP15 Register Map
Core Control Instructions
Register 13, Trace Process Identifier
CP15 RAMBIST Register Map
Exception Processing Modes
Exception Priority Order
Transfer Type Encoding
Burst Signal Encoding
Size Encoding
Protection Signal Encoding
Active Byte Lanes for a 32-Bit Little-Endian Data Bus
Active Byte Lanes for a 32-Bit Big-Endian Data Bus
Scan Chain 15 Addressing Mode Bit Order
Mapping of Scan Chain 15 Address Field to CP15
Registers
Debug State Figure Notations
CP14 Register Map
3-2
3-3
3-4
3-9
3-9
3-12
3-14
3-14
4-2
4-2
5-3
5-5
5-6
5-7
5-9
5-10
10-6
10-7
10-9
10-17
10.3
10.4
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