參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 33/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
DMA Signals
Rev. A
2-13
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
DMAMAS[1:0] DMA Memory Access Size
DMAMAS[1:0] encodes the size of DMA writes. DMA
reads are always one word wide.
Input
DMAnREQ
DMA Request
DMAnREQ is an active-LOW DMA transfer request. Tie
this input HIGH if the DMA interface is not used.
Input
DMAnRW
DMA Write not Read
DMAnRW is the DMA Read/Write signal.
Input
DMARData[31:0]
DMA Read Data
This 32-bit bus contains DMA Data read from the Data
RAM.
Output
DMAReady
DMA Ready
DMAReady is asserted HIGH when the ARM966E-S is
stalled due to a DMA Wait request. DMAReady must be
sampled HIGH before a DMA transfer to/from a
single-port Data RAM can take place.
Output
DMAWait
DMA Wait Request
DMAWait is asserted HIGH to stall the ARM966E-S
before proceeding with a DMA transfer to/from a
single-port Data RAM implementation. A HIGH on
DMAReady indicates when the ARM966E-S is stalled.
Input
Only use this signal for single-port Data RAM
implementations. Tie it LOW for dual-port Data RAM
implementations.
DMAMAS[1:0] Memory Access Size
00
01
10
11
Byte
Halfword
Word
Reserved
DMAnRW
Function
0
1
Read
Write
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