參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 131/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
About the EmbeddedICE-RT Logic
Rev. A
10-15
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
Figure 10.7 The ARM9E-S, TAP Controller, and EmbeddedICE-RT
The EmbeddedICE-RT logic comprises:
two real-time watchpoint units
two independent registers: the debug control register and the debug
status register
debug communications channel.
The Debug Control Register and the Debug Status Register provide
overall control of EmbeddedICE-RT operation.
You can program one or both watchpoint units to halt the execution of
instructions by the core. Execution halts when the values programmed
into the EmbeddedICE-RT match the values currently appearing on the
address bus, data bus, and various control signals.
Any bit can be masked so that its value does not affect the comparison.
DBGEXT[1:0]
DBGCOMMRX
DBGCOMMTX
DBGRNG[1:0]
DBGACK
DBGIEBKPT
EDBGRQ
DBGDEWPT
DBGEN
DBGTCKEN
DBGTMS
DBGTDI
DBGTDO
CLK
EmbeddedICE-RT
Processor
DBGnTRST
TAP
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