參數(shù)資料
型號： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 45/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
Processor Modes
Rev. A
3-3
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
ARM instructions are exactly one word (32 bits) and are aligned on a
four-byte boundary. THUMB instructions are exactly one halfword
(16 bits) and are aligned on a two-byte boundary.
All data operations (for example, ADD) are performed on word quantities.
Load and store operations can transfer bytes, halfwords, and words to
and from memory, automatically zero-extending or sign-extending bytes
or halfwords as they are loaded. Signed operands are in two’s
complement format.
3.4 Processor Modes
The ARM966E-S supports seven processor modes. These modes are
summarized in Table 3.2.
Mode changes occur either through software control or as a result of
external interrupts or exception processing. Most application programs
execute in User mode. The other modes, known as
privileged modes
, are
entered to service interrupts or exceptions or to access protected
resources.
Table 3.2
ARM9E-S Processor Modes
Processor Mode
Description
User (USR)
Normal program execution mode
FIQ (FIQ)
High-speed data transfer or channel process
IRQ (IRQ)
General-purpose interrupt handling
Supervisor (SVC)
Protected mode for the operating system
Abort (ABT)
Virtual memory and/or memory protection
implementation
Undefined (UND)
Software emulation of hardware coprocessors
System (SYS)
Privileged operating system tasks (architecture
version 4 only)
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