參數(shù)資料
型號(hào): ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 16/166頁
文件大小: 1145K
代理商: ARM966E-S
1-4
Introduction
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
The processor is implemented using a five-stage pipeline:
Instruction Fetch (F)
Instruction Decode (D)
Execute (E)
Data Memory Access (M)
Register Write (W)
ARM implementations are fully interlocked, so that software functions
identically across different implementations without concern for how the
pipeline is affected.
1.2.2 System Controller
The System Controller oversees the interactions between the Instruction
RAM, Data RAM, and the Bus Interface Unit. It controls internal
arbitration between the blocks and stalls the appropriate blocks when
required.
1.2.3 CP15 System Control Coprocessor
The processor core uses a set of registers in the CP15 Coprocessor to
control the functionality of the RAMs and the Write Buffer. These
registers are accessed using the coprocessor instructions MCR and
MRC.
1.2.4 Address Decoders
The address decoders determine whether a memory request accesses
the internal RAM or the Advanced High-Performance Bus (AHB)
interface. The address decoders provide a hit/miss indication to the
System Controller, which then either stalls the core if an AHB read or
unbuffered write access is required or allows execution to continue if the
access hits the RAM or is a buffered write.
1.2.5 Instruction and Data RAMs
The ARM966E-S incorporates internal instruction and data memories to
allow high-speed operation without incurring the performance penalty of
accessing the system bus or the die size penalty of a cached processor.
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