參數(shù)資料
型號： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術手冊6月1日
文件頁數(shù)： 46/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
3-4
Programmer’s Model
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
3.5 CP15 Instruction Format
System Control Coprocessor 15 (CP15) controls the operation and
configuration of the Instruction RAM, Data RAM, and write buffer. This
coprocessor is backward-compatible with the ARM7. All unused and
reserved bits should be programmed to zeros.
To read and write the configuration registers, use the MRC and MCR
instructions, respectively. These operations are only allowed in nonuser
modes; an undefined instruction trap is taken if accesses are attempted
in user mode.
Figure 3.1 shows the fields that make up the instruction format.
Figure 3.1
Coprocessor Instruction Format
Table 3.3 defines the fields within the coprocessor instruction format.
31
28 27
24 23
21 20 19
16 15
12 11
8
7
5
4
3
0
Cond
1110
opcode_1 n
CRn
Rd
1111
opcode_2 1
CRm
Table 3.3
Instruction Format Field Descriptions
Field Name
Function
Cond
ARM condition code
opcode_1
ARM opcode 1. Opcode_1 is zero for all CP15 instructions.
n
Load/store bit
0 = MRC (CP15 register read)
1 = MCR (CP15 register write)
CRn
CP15 Source/Destination register. This field determines
which configuration register is being accessed.
Rd
ARM CPU register
1111
Coprocessor number (p15)
opcode_2
ARM opcode 2
CRm
CP15 Operand register
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