參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 50/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
3-8
Programmer’s Model
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
Figure 3.4
Program Status Registers (CPSR and SPSR) Format
The N (negative), Z (zero), C (carry), V (overflow), and S (sticky) bits are
the condition code flags. The condition code flags in the CPSR can be
changed as a result of arithmetic and logical operations in the processor
and can be tested by all instructions to determine whether the instruction
is to be executed.
The S bit supports the ARM9E instruction extensions. It is set whenever
either a saturation occurs during a QADD, QDADD, QSUB, or QDSUB
instruction or when the result of an SMLAxx or SMLAWx instruction
overflows 32 bits. You must use an MRS instruction to observe the
contents of the S flag. The S flag is sticky. Once it is set, then no
subsequent instruction will reset it apart from an MSR instruction writing
to the CPSR. Refer to Appendix A for descriptions of the ARM9E
instruction extensions.
Bits [26:8] are reserved. They read as zeros and may only be written with
the same value read from the same field as the processor.
Bits [7:0] are the control bits. They change when an exception arises and
can be altered by software only when the processor is in a privileged
mode. The I bit disables IRQ interrupts when it is set. When set, the F bit
disables FIQ interrupts. When the T flag is zero, it indicates ARM
execution; when it is set, it indicates THUMB execution.
The mode bits, M[4:0], determine the mode in which the processor
operates. Table 3.4 shows the encoding of these bits. Values not shown
in the table are invalid; their results are unpredictable.
31 30 29 28 27 26
8
7
6
5
4
3
2
1
0
N
Z
C
V
S
Res
I
F
T M4 M3 M2 M1 M0
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