參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術手冊6月1日
文件頁數(shù): 52/166頁
文件大小: 1145K
代理商: ARM966E-S
3-10
Programmer’s Model
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
3.7.2.1 ID Code Register (0)
Register 0 is a read-only register that lists the core identifier. Accessing
Register 0 with the
MRC p15, 0, Rd, c0, c0, 0
instruction returns
the ID code.
ID Code Register –
The ID Code Register is a read-only identity
register that returns the LSI Logic code for this core. This code is made
up of four fields.
Implementor
[31:24]
This field contains an eight-bit value unique to LSI Logic
Corporation. Its value is 0x41.
Architecture Version
[23:16]
This field specifies the ARM9E-S architecture. Its value is
0x05 (Version 5T).
LSI Logic Core ID
[15:4]
This field contains a 12-bit value that uniquely identifies
this core. Its value is 0x966.
Revision
[3:0]
This four-bit field indicates the revision number. Its value
is 0x0.
3.7.2.2 Control Register (1)
The Control register is a read/write register that contains the control bits.
The reserved bits denoted as SBZ should be written with zeros; the
reserved bits denoted as SBO should be written with ones. All bits are
13
Trace process identifier
14
Reserved (undefined instruction)
15
Test
Table 3.5
CP15 Register Map (Cont.)
Register
Function
31
24 23
16 15
4
3
0
Implementor
Architecture Version
LSI Logic Core ID
Revision
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