參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 9/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
Contents
Rev. A
ix
Copyright 1999–2001 by LSI Logic Corporation. All rights reserved.
5.6.2
Slave Transfer Responses
5.7.1
Two-Cycle Response
5.7.2
Error Response
5.7.3
Retry Responses
5.7.4
Split Responses
Burst Operation Example
5-15
5-16
5-17
5-18
5-19
5-19
5.7
Chapter 6
Write Buffer
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Introduction
Normal Operation
Full Write Buffer
Unbuffered Writes
Read-Lock-Write
Read to Write-Posted Address
Write Buffer Nonrecoverable Error and Abort Conditions
6-1
6-2
6-2
6-3
6-3
6-3
6-3
Chapter 7
System Controller
7.1
Operation
7.2
Clock Control
7-1
7-2
Chapter 8
Tightly Coupled RAM
8.1
Tightly Coupled Memory (TCM) Overview
8.2
ARM966E-S SRAM Requirements
8.3
Enabling the SRAM
8.3.1
Using INITRAM to Enable SRAM
8.3.2
Using CP15 Control Register to Enable SRAM
8.4
ARM966E-S SRAM Wrapper
8.5
Example SRAM Interfaces
8.5.1
ONESEGX32
8.5.2
FOURSEGX32
8.5.3
FOURSEGX8
8-1
8-1
8-2
8-2
8-3
8-5
8-6
8-7
8-7
8-8
Chapter 9
External Coprocessor Interface
9.1
Overview
9.2
Coprocessor Instruction Execution
9.2.1
LDC/STC Instructions
9-1
9-2
9-2
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