參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 107/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
ARM966E-S Microprocessor Core Technical Manual
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
9-1
Chapter 9
External Coprocessor
Interface
This chapter describes the ARM966E-S external coprocessor interface.
The ARM966E-S connects to on-chip coprocessors through this
interface. This interface supports all types of coprocessor instructions.
This chapter contains the following sections:
Section 9.1, “Overview”
Section 9.2, “Coprocessor Instruction Execution”
Section 9.3, “Privileged Instructions”
Section 9.4, “Stalling and Interrupts”
9.1 Overview
Coprocessors determine which instructions they need to execute by a
pipeline follower
in the coprocessor. As each instruction arrives from
memory, it enters both the ARM9E-S pipeline and the coprocessor’s
pipeline. To avoid a critical path for the instruction being latched by the
coprocessor, the coprocessor’s pipeline operates one clock cycle later
than the ARM9E-S core pipeline. However, the ARM966E-S also
includes a mechanism that stalls the pipeline so the processor can catch
up with the external coprocessor pipeline. So, in effect, both pipelines are
synchronized. The ARM9E-S core informs the coprocessor when
instructions move from decode into execute, and whether the instruction
needs to be executed.
To enable coprocessors to continue execution of coprocessor data
operations while the ARM9E-S core pipeline is stalled, the coprocessor
receives the CLK clock, and a clock enable signal CPCLKEN. If
CPCLKEN is LOW on the rising edge of CPCLK, then the ARM9E-S core
pipeline is stalled and the coprocessor pipeline should not advance.
Figure 9.1 indicates the timing for these signals and when the
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