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參數(shù)資料
| 型號(hào)： | ARM966E-S |
| 英文描述： | ARM966E-S Microprocessor Core preliminary technical manual 6/01 |
| 中文描述： | ARM966E - ?微處理器核的初步技術(shù)手冊(cè)6月1日 |
| 文件頁(yè)數(shù)： | 135/166頁(yè) |
| 文件大?。?/td> | 1145K |
| 代理商： | ARM966E-S |
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The Debug Communications Channel
Rev. A
10-19
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
breakpoint or watchpoint. If the ARM966E-S takes a Prefetch Abort as a
result of a breakpoint or watchpoint, then the bit is set. If on a particular
instruction or data fetch, both the debug abort and external abort signals
are asserted, the external abort takes priority and the DbgAbt bit is not
set. You can read or write the DbgAbt bit by means of MRC or MCR
instructions.
This bit can be used by a real-time debug aware abort handler. This
handler examines the DbgAbt bit to determine whether the abort is
externally or internally generated. If the DbgAbt bit is set, the abort
handler initiates communication with the debugger over the
communications channel.
10.9.4 Using the Communications Channel
Messages can be sent and received using the communications channel.
10.9.4.1 Sending a Message to the Debugger
When the processor wishes to send a message to the debugger, it must
check to see if the Communications Data Write Register is free for use.
The processor reads the Debug Communications Control Register to
check the status of the W bit.
If W bit is cleared, the Communications Data Write Register is free
for use.
If the W bit is set, previously written data is not read by the debugger.
The processor must continue to poll the Debug Communications
Control Register until the W bit is cleared.
When the W bit is cleared, a message is written by a register transfer to
coprocessor 14. Because the data transfer occurs from the processor to
the Communications Data Write Register, the W bit is set in the Debug
Communications Control Register.
The debugger sees both the R and W bits when it polls the Debug
Communications Control Register through the JTAG interface. When the
debugger sees that the W bit is set, it can read the Communications Data
Write Register, and scan the data out. The action of reading this data
register clears the W bit in the Debug Communications Control Register.
At this point, the communications process can begin again.
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