參數(shù)資料
型號(hào)： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊(cè)6月1日
文件頁數(shù)： 109/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
Coprocessor Instruction Execution
Rev. A
9-3
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
Figure 9.2
LDC/STC Cycle Timing
As with all other instructions, the ARM9E-S core performs the main
decode off the rising edge of the clock during the decode stage. From
this, the core commits to executing the instruction and so performs an
instruction fetch. The coprocessor’s instruction pipeline keeps in step
with the ARM9E-S core by monitoring nCPMREQ, which is a latched
copy of the ARM9E-S core instruction memory request signal InMREQ.
Whenever nCPMREQ is LOW, an instruction fetch is occurring and
CPINSTR is updated with the fetched instruction in the next cycle. Thus
the instruction currently on CPINSTR should enter the decode stage of
the coprocessor pipeline, and the instruction in the decode stage of the
coprocessor’s pipeline should enter its execute stage.
During the execute stage, the condition codes are combined with the
flags to determine whether the instruction really executes or not. The
output CPPASS is asserted HIGH if the instruction in the execute stage
of the coprocessor pipeline is a coprocessor instruction and has passed
its condition codes. If a coprocessor instruction stalls, then CPPASS is
asserted on every cycle until the coprocessor instruction is executed. If
an interrupt occurs during stalling then CPPASS is driven LOW and the
coprocessor should stop the coprocessor instruction execution.
GO
GO
LAST Ignored
CPCLK
nCPMREQ
CPPASS
CPLATECANCEL
CHSDE[1:0]
CHSEX[1:0]
CPDOUT[31:0]
LDC
CPDIN[31:0]
STC
GO
Decode Execute Execute Execute Execute Memory
GO
GO
Write
GO
LAST
Processor
Pipeline
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