參數(shù)資料
型號(hào): ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊(cè)6月1日
文件頁數(shù): 79/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
AHB Interface Signals
Rev. A
5-9
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
address boundaries (HADDR[1:0] = 00), halfword transfers must be
aligned to halfword address boundaries (HADDR0 = 0).
For transfers that are narrower than the width of the bus, for example, a
16-bit transfer on a 32-bit bus, then the bus master only has to drive the
appropriate byte lanes. The slave is responsible for selecting the write
data from the correct byte lanes. Table 5.5 and Table 5.6 show which
byte lanes are active for little-endian and big-endian systems,
respectively. Burst transfers that have a transfer size less than the width
of the data bus have different active byte lanes for each beat of the
transfer.
Table 5.5
Active Byte Lanes for a 32-Bit Little-Endian Data Bus
Transfer
Size
Address
Offset
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
Word
0
x
x
x
x
Halfword
0
x
x
Halfword
2
x
x
Byte
0
x
Byte
1
x
Byte
2
x
Byte
3
x
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