參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 71/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
ARM966E-S Microprocessor Core Technical Manual
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
5-1
Chapter 5
AHB Interface Unit
This chapter describes the operation of the Advanced High-Performance
Bus (AHB) Interface Unit. It contains the following sections:
Section 5.1, “Overview”
Section 5.2, “AHB Interface Signals”
Section 5.3, “AHB Clocking”
Section 5.4, “AHB Operation”
Section 5.5, “Basic Transfers”
Section 5.6, “Burst Operations”
5.1 Overview
The AHB is a high-performance, burst-based bus protocol that
complements the lower level AMBA Advanced System Bus (ASB) and
APB protocols. The AHB bus supplies the needed requirements for
high-performance/high clock frequency systems. This bus can handle the
following:
burst transfers
single-cycle bus master handover
single clock edge operation
non-3-state implementation
The AHB bus protocol is used with a central multiplexer interconnection
scheme. From this scheme, all bus masters drive out the address and
control signals indicating the transfer they wish to perform. The arbiter
determines which master has its address/control signals routed to all of
the slaves. A central decoder is also required to control the read data
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