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| 型號(hào)： | ARM966E-S |
| 英文描述： | ARM966E-S Microprocessor Core preliminary technical manual 6/01 |
| 中文描述： | ARM966E - ?微處理器核的初步技術(shù)手冊6月1日 |
| 文件頁數(shù)： | 73/166頁 |
| 文件大?。?/td> | 1145K |
| 代理商： | ARM966E-S |
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AHB Interface Signals
Rev. A
5-3
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
5.2.1 Transfer Types
Every transfer is classified into one of four different types, as determined
by the HTRANS[1:0] signals.
The first transfer of any burst is nonsequential; the address is unrelated
to the previous transfer. The remaining transfers in a burst are sequential;
the address is related to the previous transfer. Single transfers on the bus
are treated as bursts of one, and thus the transfer type is nonsequential.
The IDLE transfer type is used when a bus master is granted the bus,
but does not wish to perform a data transfer. Slaves must provide a zero
wait state OKAY response to IDLE transfers.
The BUSY transfer type allows bus masters to insert idle cycles in the
middle of a burst of transfers. This transfer type indicates that the bus
master is continuing with a burst, but the next transfer cannot take place
immediately.
When a master uses the BUSY transfer type, the address and control
signals must reflect the next transfer in the burst. The master must
always perform this transfer and cannot cancel it at a later point in time.
Slaves must provide a zero wait state OKAY response in the same way
that they respond to IDLE transfers.
Table 5.1
Transfer Type Encoding
HTRANS[1:0]
Transfer
Type
Description
00
IDLE
Idle transfer is used when a bus master is granted the bus, but does not
transfer data.
01
BUSY
Busy transfer is used to insert an idle cycle in the middle of a burst of
transfers.
10
NONSEQ
Nonsequential transfer indicates the first transfer of a burst or a single
transfer.
11
SEQ
Sequential transfer is used for subsequent transfers in a burst. The
control information is identical to the previous transfer. The address is
equal to the address of the previous transfer plus the size (in bytes). For
wrapping bursts, the address of the transfer wraps at the address
boundary equal to the size (in bytes) multiplied by the number of beats
in the transfer (either 4, 8, or 16).
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