參數(shù)資料
型號： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 35/166頁
文件大小： 1145K
代理商： ARM966E-S
Debug Signals
Rev. A
2-15
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
DBGIR[3:0]
Tap Controller Instruction Register
These outputs reflect the current instruction loaded into
the TAP controller instruction register. They change when
the TAP state machine is in the UPDATE_IR state on the
rising edge of CLK when DBGTCKEN is asserted.
Output
DBGnTDOEN DBGTDO 3-State Enable
When LOW, this signal indicates there is serial data on
the DBGTDO output. DBGnTDOEN can be used as the
output enable on a packaged part’s DBGTDO pin.
Output
DBGnTRST
Not Test Reset
This active-LOW input is the internally synchronized reset
signal for the EmbeddedICE internal state.
Input
DBGRNG[1:0] Watchpoint Register Match
These outputs indicate that the corresponding
EmbeddedICE Watchpoint register has matched the
conditions currently present on the address, data, and
control buses. These signals are independent of the state
of the watchpoint’s enable control bit.
Output
DBGRQI
Internal Debug Request
This signal is the debug request signal presented to the
processor core’s debug logic. It is the ANDing of
EDBGRQ as presented to the ARM966E-S and bit 1 of
the Debug Control Register.
Output
DBGSCREG[4:0]
Scan Chain Register
These outputs reflect the ID number of the scan chain
currently selected by the TAP controller. They change
when the TAP state machine is in the UPDATE_DP state
on the rising edge of CLK when DBGTCKEN is asserted.
Output
DBGSDIN
Boundary Scan Serial Input Data
This output contains the serial data for an external scan
chain.
Output
DBGSDOUT
Boundary Scan Serial Output Data
DBGSDOUT is the serial data input from an external
scan chain. When an external scan chain is not
implemented, tie this signal LOW.
Input
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