參數(shù)資料
型號(hào)： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 59/166頁
文件大?。?/td> 1145K
代理商： ARM966E-S
Registers
Rev. A
3-17
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
this register is cleared to allow testing of the full instruction memory.
However, it can be set to a nonzero value to limit testing to only a portion
of instruction memory.
When the Instruction BIST Pause bit is set, a write to this register sets
the Instruction Pause Address. When BIST testing is paused, the Pause
address is held at the instruction memory RAM address input.
CP15 Instruction BIST Test/Pause Write Data Register –
The
function of this write-only register depends on the setting of the IPause
bit in the CP15 BIST Control register.
When the Instruction BIST Pause bit is cleared, a write to this register
sets the Instruction BIST Data pattern (IBISTTestData). The BIST
algorithm uses IBISTTestData and its inverse pattern for instruction
memory BIST testing.
When the Instruction BIST Pause bit is set and BIST operation is
paused, data written to this register is placed in the instruction memory
at the IBIST Pause Address.
CP15 Instruction BIST Fail Address Register –
This read-only
register contains the address of the first detected instruction memory
failure. This register is valid when the Instruction RAM BIST Fail bit is set
in the CP15 BIST Control register.
Because ARM BIST was not implemented, this register is hardcoded to
0x00000000.
CP15 Instruction BIST Fail/Pause Read Data Register –
The
function of this read-only register depends on the setting of the IPause
bit in the CP15 BIST Control register.
Because ARM BIST was not implemented, this register has been
hardcoded to 0x00000000.
31
0
IBIST Test Data/IBIST Pause Write Data
31
26 25
0
Reserved
IBIST Fail Address
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