參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù): 91/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
ARM966E-S Microprocessor Core Technical Manual
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
6-1
Chapter 6
Write Buffer
This chapter describes the ARM966E-S Write Buffer.
This chapter contains the following sections:
Section 6.1, “Introduction”
Section 6.2, “Normal Operation”
Section 6.3, “Full Write Buffer”
Section 6.4, “Unbuffered Writes”
Section 6.5, “Read-Lock-Write”
Section 6.6, “Read to Write-Posted Address”
Section 6.7, “Write Buffer Nonrecoverable Error and Abort
Conditions”
6.1 Introduction
The ARM966E-S Write Buffer enhances system performance. It
decouples the processor from a slower memory interface during
processor writes. The Write Buffer allows the core to perform writes
without waiting for access to the AHB bus.
The Write Buffer consists of a 12-entry FIFO. Each entry can be either
address or data, where the use of each entry is specified by an
address/data flag. Each address entry is tagged with the size of the
transfer as indicated by the ARM9E-S processor core (byte, halfword, or
word).
The Write Buffer is flushed at reset. Any entries still in the buffer when
reset is asserted are lost. To enable the Write Buffer, write to CP15
Register 1. To drain the Write Buffer, write to CP15 Register 7.
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