參數(shù)資料
型號： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 110/166頁
文件大小： 1145K
代理商： ARM966E-S
9-4
External Coprocessor Interface
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
The CPLATECANCEL output is used to cancel a coprocessor instruction
when the instruction preceding it causes a data abort. This output is valid
on the rising edge of CLK on the cycle after the coprocessor instruction’s
first execute cycle.
On the rising edge of the clock, the ARM9E-S processor core examines
the coprocessor handshake signals CHSDE[1:0] and CHSEX[1:0]. If a
new instruction is entering the execute stage in the next cycle, then the
core examines CHSDE[1:0]. If the coprocessor instruction currently in
execution requires another execute cycle, then the core examines
CHSEX[1:0]. The handshake signals encode one of four states:
ABSENT
If there is no coprocessor attached that can execute the coprocessor
instruction, then the handshake signals indicate the ABSENT state,
and the ARM9E-S core takes the undefined instruction trap.
WAIT
If there is a coprocessor attached that can handle the instruction, but
not immediately, then the coprocessor handshake signals are driven
to indicate that the ARM9E-S core should stall until the coprocessor
can catch up. In this case, the ARM9E-S core loops in an idle state
waiting for CHSEX[1:0] to be driven to another state, or for an
interrupt to occur. If CHSEX[1:0] changes to ABSENT then the
undefined instruction trap is taken. If CHSEX[1:0] changes to GO or
LAST, then the instruction proceeds as described below. If an
interrupt occurs, then the ARM9E-S core is forced out of the stalled
state. This condition is indicated to the coprocessor by a LOW
transition on CPPASS. The instruction is restarted at a later time.
The coprocessor should not commit to the instruction (change any of
the coprocessor’s states) until it has seen CPPASS HIGH when the
handshake signals indicate the GO or LAST condition.
GO
The GO state indicates that the coprocessor can execute the
instruction immediately, and that it requires another cycle of
execution. Both the ARM9E-S core and the coprocessor must also
consider the state of the CPPASS signal before actually committing
to the instruction. For an LDC or STC instruction, the coprocessor
instruction drives the handshake signals with GO when two or more
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