參數(shù)資料
型號： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 54/166頁
文件大小： 1145K
代理商： ARM966E-S
3-12
Programmer’s Model
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
WB
Write Buffer Enable
This bit determines whether the write buffer is enabled or
not. At reset, the write buffer is disabled.
3
D
Data Memory Enable Bit
This bit determines whether data accesses will access
the Data RAM or the AHB. At reset, this bit takes on the
value of the INITRAM pin.
2
3.7.2.3 Core Control Register (7)
The Core Control register is a write-only register. Writes to this register
can drain the write buffer, or cause a wait for interrupts. A read of this
register returns an unspecified value. Table 3.6 shows the valid write
instructions to this register with their corresponding functions.
Drain Write Buffer –
Coprocessor 15 can stall instruction execution
until the write buffer is emptied. This operation is useful in real-time
applications where the processor needs to be sure that a write to a
peripheral has completed before program execution continues. An
example is where a peripheral in a bufferable region is the source of an
interrupt. Once the interrupt has been serviced, the request must be
removed before interrupts can be re-enabled. The processor can be sure
of the removal if a drain write-buffer operation separates the store to the
peripheral and the enable interrupt functions.
WB
Description
0
1
Write Buffer disabled
Write Buffer enabled
D
Description
0
1
Data RAM accessed
AHB accessed
Table 3.6
Core Control Instructions
ARM Instruction
Data
Function
MCR p15, Rd, c7, c10, 4
SBZ
Drain Write Buffer
MCR p15, Rd, c7, c0, 4
SBZ
Wait For Interrupt
MCR p15, Rd, c15, c8, 2
SBZ
Wait For Interrupt (StrongARM backward
compatibility)
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