參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術手冊6月1日
文件頁數(shù): 40/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
2-20
Signal Descriptions
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
present on the address, data, and control buses. This
signal is independent of the state of the watchpoint’s
enable control bit.
ETMWDATA[31:0]
ETM Write Data
This 32-bit bus contains ETM write data.
Output
ETMINSTRVALID
ETM Instruction Valid
The ARM966E-S asserts this output HIGH to indicate the
current instruction is valid for the ETM.
Output
ETMPROCID[31:0]
ETM Process ID
This 32-bit output contains the Process ID for the ETM.
Output
ETMPROCIDWR]
ETM Process ID Write
This output is asserted when ETMPROCID is written.
Output
FIFOFULL
ETM FIFO FULL
This input is asserted when the ETM FIFO is full. Tie this
signal LOW if an ETM is not used.
Input
TAPID[31:0]
Boundary Scan ID Code
This bus specifies the ID Code value shifted out on
DBGTDO when the IDCODE instruction enters the TAP
Controller.
Input
2.8 Miscellaneous Signals
BIGENDOUT
Big Endian
When this output is HIGH, the ARM966E-S is in
big-endian mode (byte 0 is the most-significant bit). When
this output is LOW, the ARM966E-S is in little-endian
mode.
Output
This output is a static configuration signal. It must remain
at one value from reset or be changed using a carefully
constructed code sequence to avoid software problems.
CLK
System Clock
CLK is the ARM966E-S system clock. CLK can be
stretched in either state (held HIGH or LOW).
Input
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