參數(shù)資料
型號： ARM966E-S
英文描述： ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述： ARM966E - ?微處理器核的初步技術(shù)手冊6月1日
文件頁數(shù)： 26/166頁
文件大小： 1145K
代理商： ARM966E-S
2-6
Signal Descriptions
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
states prior to decoding what response to give, then it
must drive the response to OKAY.
HSIZE[2:0]
Transfer Size
This output indicates the size of the transfer, which is
typically byte (8 bits), halfword (16 bits), or word (32 bits).
Output
HRESP[1:0]
Transfer
Response
Description
00
OKAY
When HREADY is HIGH, the
transfer has completed.
This response shows an error
has occurred. The error
condition must be signaled to the
bus master so that it is aware the
transfer was unsuccessful.
01
ERROR
A two-cycle response is required
for an Error condition.
The Retry response shows the
transfer is not complete, so the
bus master should retry the
transfer. The master will continue
to retry the transfer until it
completes.
10
RETRY
A two-cycle RETRY response is
required.
The Split response indicates the
transfer has not yet completed
successfully. The bus master
must retry the transfer when it is
next granted access to the bus.
The slave will request access to
the bus on behalf of the master
when the transfer can complete.
11
SPLIT
A two-cycle SPLIT response is
required.
HSIZE[2:0]
Transfer Size Description
000
001
010
011–111
8 bits
16 bits
32 bits
Reserved
Byte
Halfword
Word
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