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| 型號(hào)： | ARM966E-S |
| 英文描述： | ARM966E-S Microprocessor Core preliminary technical manual 6/01 |
| 中文描述： | ARM966E - ?微處理器核的初步技術(shù)手冊(cè)6月1日 |
| 文件頁(yè)數(shù)： | 111/166頁(yè) |
| 文件大?。?/td> | 1145K |
| 代理商： | ARM966E-S |
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Coprocessor Instruction Execution
Rev. A
9-5
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
words still need to be transferred. When only one more word is
required, the coprocessor drives the handshake signals with LAST.
LAST
If an LDC or STC instruction is for more than one item of data, then
after stalling, the coprocessor might drive the coprocessor
handshake signals with a number of GO states, and in the cycle
LAST, where LAST indicates that the next transfer is the final one. If
there is only one transfer then the sequence would be:
[WAIT,[WAIT,...]],LAST.
9.2.2 MCR/MRC Instructions
These cycles look very similar to STC/LDC cycles. Figure 9.3 shows an
example with a stall (WAIT) state. First nCPMREQ is driven LOW to
denote that the instruction on CPINSTR is entering the decode stage of
the pipeline. This low state causes the coprocessor to decode the new
instruction and drive CHSDE[1:0] as required. In the next cycle
nCPMREQ is driven LOW to denote that the instruction has now been
issued to the execute stage. If the condition codes pass (thus the
instruction is to be executed), then CPPASS is driven HIGH and the
CHSDE[1:0] handshake bus is examined (it is ignored in all other cases).
For any successive execute cycles, the CHSEX[1:0] handshake bus is
examined. When the LAST condition is observed, the instruction is
committed. In the case of an MCR instruction, the CPDOUT[31:0] bus is
driven with the register data during the coprocessor write stage. In the
case of an MRC instruction, CPDIN[31:0] is sampled at the end of the
ARM9E-S memory stage and is written to the destination register during
the next cycle.
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