參數(shù)資料
型號: ARM966E-S
英文描述: ARM966E-S Microprocessor Core preliminary technical manual 6/01
中文描述: ARM966E - ?微處理器核的初步技術手冊6月1日
文件頁數(shù): 117/166頁
文件大?。?/td> 1145K
代理商: ARM966E-S
ARM966E-S Microprocessor Core Technical Manual
Rev. A
Copyright 1999-2001 by LSI Logic Corporation. All rights reserved.
10-1
Chapter 10
Debug
This chapter describes the operation of the ARM966E-S debug interface.
The debug interface is based on IEEE Std 1149.1-1990. This chapter
contains the following sections:
Section 10.1, “Debug Systems”
Section 10.2, “About the Debug Interface”
Section 10.3, “Scan Chain 15”
Section 10.4, “Breakpoints, Watchpoints, and External Debug
Requests”
Section 10.5, “ARM9E-S Clock Domains”
Section 10.6, “Determining the Core and System States”
Section 10.7, “About the EmbeddedICE-RT Logic”
Section 10.8, “Disabling the EmbeddedICE-RT Logic”
Section 10.9, “The Debug Communications Channel”
Section 10.10, “Real-Time Debug”
A more detailed description of the ARM9E-S debug features and JTAG
interface is provided in Appendix D, Debug in Depth, of the
ARM9E-S
Technical Reference Manual.
10.1 Debug Systems
The ARM966E-S forms one component of a debug system that
interfaces from the high-level debugging you perform to the low-level
interface the ARM966E-S supports. Figure 10.1 shows a typical debug
system.
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